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X24257V14I-2.5 Datasheet(PDF) 8 Page - Xicor Inc. |
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X24257V14I-2.5 Datasheet(HTML) 8 Page - Xicor Inc. |
8 / 19 page X24257 – Preliminary Information Characteristics subject to change without notice. 8 of 19 REV 1.1.1 10/15/00 www.xicor.com Figure 9. Random Read Sequence Figure 10. Sequential Read Sequence Signals from the Master SDA Bus Signals from the Slave S T A R T S T O P A C K A C K A C K 0 S T A R T 1 Data A C K S P S 10 1 0 Slave Address Byte 1 Word Address Byte 0 Word Address Slave Address 0 S1S0 S S T O P A C K A C K A C K A C K (1) (2) (n–1) (n) 1 (n is any integer greater than 1) P Signals from the Master SDA Bus Signals from the Slave Slave Address Data Data Data Data S1S0 CONTROL REGISTER (CR) The Control Register is located in an area logically separated from the array and is only accessible via a byte write to the register address of FFFFH. The Con- trol Register is physically part of the array. The Control Register can only be modified by perform- ing a byte write operation directly to the address of the register and only one data byte is allowed for each reg- ister write operation. Prior to initiating a nonvolatile write to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. The user must issue a stop, after sending this byte to the register, to initiate the high voltage cycle that writes BP2, BP1, BP0 and WPEN to the nonvolatile bits. The part will not acknowledge any data bytes written after the first byte is entered. A stop must also be issued after a volatile register write operation to put the device into Standby. After a write to the CR, the address counter contents are undefined. The state of the Control Register can be read by per- forming a random read at the address of the register at any time. Only one byte is read by the register read operation. The part will reset itself after the first byte is read. The master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. After the read of the CR, the address counter contents are reset to zero, but the user will be told these bits are undefined and instructed to do a random read. Table 1. Control Register RWEL: Register Write Enable Latch The RWEL bit must be set to “1” prior to a write to Con- trol Register. WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeros to the other bits of the control register. Once set, WEL remains set until either it is reset to 0 (by writing a “0” to 76 5 4 321 0 WPEN X X BP1 BP0 RWEL WEL BP2 |
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