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MK3732-08RI Datasheet(PDF) 2 Page - Integrated Circuit Systems |
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MK3732-08RI Datasheet(HTML) 2 Page - Integrated Circuit Systems |
2 / 4 page MK3732-08 ADSL Clock Source MDS 3732-08 C 2 Revision 091201 Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408) 295-9800 tel • (408) 295-9818 fax • www.icst.com Pin Descriptions Key: I(PU) = Input with internal pull-up resistor; TI = Tri-level Input; O = Output; P = Power Supply Connection; VI = Analog Voltage Input; XI, XO = Crystal Pins. Pin Assignment Number Name Type Description 1 X1 XI Crystal connection. Connect to a pullable crystal of 17.664 MHz or 24.576 MHz.. 2, 19 NC - No Connect. Do not connect anything to this pin. 3, 4, 5 VDD P Power Supply. Connect to +3.3V. 6 VIN VI Voltage Input to VCXO. Zero to 3.3V signal which controls the VCXO frequency. 7, 8, 9 GND P Connect to ground. 10 PD I(PU) Power Down active low. Turns entire chip off, clocks stop low. 11 CLK1 O Clock Output #1 per table above. 12 CLK2 O Clock Output #2 per table above. 13 S2 I(PU) Select input #2. Selects outputs per table above. 14 OE I(PU) Output Enable. Tri-states outputs when low. 15 S0 TI Select input #0. Selects outputs per table above. 16 REFEN I(PU) Reference Clock Enable. Enables REF Output when low. Connect to VDD for lowest jitter. 17 REF O Reference Clock Output. This is the crystal oscillator output clock. 18 S1 I(PU) Select input #1. Selects outputs per table above. 20 X2 XO Crystal connection. Connect to a pullable crystal of 17.664 MHz or 24.576 MHz. External Components The MK3732-08 requires a minimum number of external components for proper operation. Decoupling capacitors of 0.01µF should be connected between VDD and GND pins 3 and 7, pins 4 and 8, and pins 5 and 9, as close to the MK3732-08 as possible. A series termination resistor of 33 Ω may be used for each clock output. The input crystal must be connected as close to the chip as possible. The input crystal should be a fundamental mode, parallel resonant, pullable, AT cut. S2 S1 S0 Input CLK1 CLK2 0 0 0 24.576 * 2.208 OFF 0 0 M 17.664 20.00 OFF 0 0 1 17.664 20.19 35.328 0 1 0 17.664 70.66 35.328 0 1 M 17.664 70.66 35.328 0 1 1 17.664 58.88 35.328 1 0 0 17.664 35.328 52.992 1 0 M 17.664 2.208 35.328 1 0 1 17.664 20.19 OFF 1 1 0 17.664 4.04 35.328 1 1 M 17.664 35.328 61.82 1 1 1 17.664 35.328 56.52 0=connect directly to GND; M=leave unconnected (floating); 1=connect directly to VDD * In this mode, 12.288 MHz is present on REF Clock Select Table Consult ICS for recommended suppliers. IMPORTANT - Consult the Application Note MAN05 for layout guidelines. REFEN OE S0 CLK2 16 15 14 13 12 11 17 18 1 2 3 4 5 6 7 8 NC VDD X2 X1 VDD GND VIN GND REF S2 NC S1 VDD 20 19 9 10 PD GND CLK1 20 pin (150 mil) SSOP |
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