HLX6228

6

TAVAVR

Address Read Cycle Time

32

ns

TAVQV

Address Access Time

32

ns

TAXQX

Address Change to Output Invalid Time

3

ns

TSLQV

Chip Select Access Time

35

ns

TSLQX

Chip Select Output Enable Time

5

ns

TEHQV

Chip Enable Access Time

35

ns

TEHQX

Chip Enable Output Enable Time

5

ns

TELQZ

Chip Enable Output Disable Time

13

ns

TGLQV

Output Enable Access Time

12

ns

TGLQX

Output Enable Output Enable Time

0

ns

TGHQZ

Output Enable Output Disable Time

9

ns

READ CYCLE AC TIMING CHARACTERISTICS (1, 2)

Worst Case (4)

Symbol

Parameter

Typical

-55 to 125

Units

(3)

Min

Max

(1) Key Note: This part must be Read controlled using the NCS pin: it requires that NCS returns to a high state for at least 5ns whenever there is

an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched.

The part must must be controlled in this fashion to meet the timing specifications defined.

(2) Test conditions: input switching levels,VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the

Tester AC Timing Characteristics table, capacitive output loading C

TGHQZ. For C

(3) Typical operating conditions: VDD=3.3 V, TA=25

°C, pre-radiation.

(4) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA= -55

°C to 125°C, post total dose at 25°C.

HIGH

IMPEDANCE

NCS

NOE

DATA VALID

CE

ADDRESS

(NWE = high)

DATA OUT