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ATR2406-DEV-KIT Datasheet(PDF) 7 Page - ATMEL Corporation |
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ATR2406-DEV-KIT Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 20 page 7 ATR2406 [Preliminary] 4779F–ISM–09/04 5.2 RSSI output voltage, monotonic over range -96 dBm to -36 dBm with -33 dBm at RF input with -96 dBm at RF input V RSSI 1.9 0.3 V V 5.3 Wake-up time from power-up signal to correct RSSI output T on 40 µs 6VCO 6.1 Oscillator frequency Over full temperature range (1) 2400 2483 MHz 6.2 Frequency control voltage range V VTUNE 0.5 V CC - 0.5 V 6.3 VCO tuning input gain G VCO 150 MHz/V 7 Synthesizer 7.1 External reference input frequency D7 = 0 D7 = 1 REF_CLK 10.368 13.824 MHz MHz 7.2 Sinusoidal input signal level (RMS value) AC coupled sinewave REF_CLK 250 500 mV RMS 7.3 Scaling factor prescaler S PSC 32/33 7.4 Scaling factor main counter S MC 86/87/88/89 7.5 Scaling factor swallow counter S SC 031 8 Phase Detector 8.1 Phase detector comparison frequency f PD 1728 kHz 9 Charge-pump Output 9.1 Charge-pump output current V CP = 1/2 VCC I CP ±2 mA 9.2 Leakage current V CP = 1/2 VCC I L ±100 pA 10 Timing Conditions (1)(2) 10.1 Transmit to Receive time TX →RX-time 100 µs 10.2 Receive to Transmit time RX →TX-time 100 µs 10.3 Channel switch time CS-time 350 µs 10.4 Power down to Transmit PD →TR-time 450 µs 10.5 Power down to Receive PD →RX-time 400 µs 10.6 Programming register PRR-time 3 µs 10.7 PLL settling time PLL set-time 350 µs 11 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE 11.1 HIGH-level input voltage Logic 1 V IH 1.4 3.4 V 11.2 LOW-level input voltage Logic 0 V IL -0.3 +0.4 V 11.3 HIGH-level output voltage Logic 1 V OH 3.4 V 11.4 LOW-level output voltage Logic 0 V OL 0V 11.5 Input bias current Logic 1 or logic 0 I bias -5 +5 µA 11.6 3-wire bus clock frequency f CLKmax 10 MHz Electrical Characteristics (Continued) VS = 3.6 V with AUX regulator, Tamb = 25°C, unless otherwise specified No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Notes: 1. Measured and guaranteed only on the Atmel evaluation board, including PCB and balun filter. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of loop filter. For further information refer to Application Note. |
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