W523AXXX

Publication Release Date: May 20, 2003

- 11 -

Revision A3

To place the W523Axxx in CPU mode, program the code according to the following example.

W523A015

CPU; Reserved word, used as a directive to notify the compiler for post processing.

LED1

FREQ2

POI:

LD MODE0,XX1XX0XXB ;bit2=0 BUSY

LD EN0, 0x00

H5+voice1+T5

END

34: ; Direct trigger or CPU interrupt.

H5+voice2+T5

END

The defaulted operating mode in W523Axxx is normal mode (or manual trigger mode), which is

identified by the "Normal" and "CPU" option control. To enter the CPU mode, the "CPU" declaration

must be inserted in the declaration region of program (*.out). In CPU mode, the bit MODE0.2, which is

defined as STPA or BUSY selection for the STPA/BUSY pin, will be selected as "0" (BUSY output)

automatically by the compiler unless otherwise specified explicitly by the STPA directive. The CPU,

STPA, and BUSY directives can appear only in the first paragraph of the *.out files so that the

compiler will automatically interpret them as Stop definitions in the POI interrupt vector. If these

directives are placed elsewhere, an error message will be issued during the compilation process.

In the program example shown above, the external

µC will transfer one byte data "34" to W523Axxx.

The number 34 (Decimal) is equal to 00100010b (Binary). The interface timing is shown below.

TG1

TG2

(Data)

(Clock)

010001

0

0

MSB

LSB

<1>

<2>

<3>

<4>

DEB

T

CRD

T

<1> When TG1 is pulled low, the W523Axxx stops playing voice or executing instruction and waits for data from

the external

µC.

<2> If TG1 is debounced OK, the W523Axxx will clear the CPU receiving buffer.

<3> 8-bit data are transferred by TG1 (Data) and TG2 (Clock). LSB is sent firstly.

<4> TG1 returns to high and starts the CPU interrupt service. In this case W523A015 will play the

H51+voice2+T51 sections and the STPA/BUSY pin is pulled high during the playing period.