W523AXXX

Publication Release Date: May 20, 2003

- 7 -

Revision A3

5.1.3 PAGE Register

BIT

7

6

5

4

3

2

1

0

PAGE

-

-

-

PG4

PG3

PG2

PG1

PG0

The bits 0 ~ 4 in PAGE register are used for page selection. Once the page mode being defined

(referring to the below section of “Option Control Function”), the working page is selected by the bits 0

~ 4 in the PAGE register. Hence, the user can execute "LD PAGE, value" instruction to change the

working page of the voice entry group. Not all of the bits 0 ~ 4 of PAGE register are used in different

page mode. They are listed as below table:

PAGE MODE

PG4

PG3

PG2

PG1

PG0

1-page

×

×

×

×

×

8-page

×

×

√

√

√

16-page

×

√

√

√

√

32-page

√

√

√

√

√

Where "

×" means don′t care and "√" means must be set properly.

5.1.4 EN Register (W523A012 ~ W523A120)

BIT

7

6

5

4

3

2

1

0

EN0

X

X

TG2R

TG1R

X

X

TG2F

TG1F

EN1

X

X

TG6R

TG5R

X

X

TG6F

TG5F

EN Register (W523A008, W523A010)

BIT

7

6

5

4

3

2

1

0

EN0

TG4R

TG3R

TG2R

TG1R

TG4F

TG3F

TG2F

TG1F

EN0 or EN1 is an 8-bit register that stores the rising/falling edge enable or disable status information

for all trigger pins, which determines whether each trigger pin is retriggerable, non-retriggerable,

overwrite, or non-overwrite. The 8-bit structure of this register and the rising or falling edge of the

triggers corresponding to each bit are shown above. “X” indicates a “don’t care” bit.

The TG1, 2, 5, 6 represents triggers 1, 2, 5 and 6 respectively; the “R” represents the rising edge; and

“F” represents the falling edge. When any one of the eight bits is set to “1”, the rising or falling edge of

the corresponding trigger pin can be enabled, interrupting the current state.

5.1.5 STOP Register

BIT

7

6

5

4

3

2

1

0

STOP

X

X

X

STE

STD

STC

STB

STA