W159
Document #: 38-07163 Rev. *A
Page 2 of 11
Overview
The W159 is designed to provide the essential frequency
sources to work with advanced multiprocessing Intel® archi-
tecture platforms. Split voltage supply signaling provides 2.5V
and 3.3V clock frequencies operating up to 133 MHz.
From a low-cost 14.31818-MHz reference crystal oscillator,
the W159 generates 2.5V clock outputs to support CPUs, core
logic chip set, and Direct RDRAM clock generators. It also pro-
vides skew-controlled PCI and IOAPIC clocks synchronous to
CPU clock, 48-MHz Universal Serial Bus (USB) clock, and rep-
licates the 14.31818-MHz reference clock.
All CPU, PCI, and IOAPIC clocks can be synchronously mod-
ulated for spread spectrum operations. Cypress employs pro-
prietary techniques that provide the maximum EMI reduction
while minimizing the clock skews that could reduce system
timing margins. The use of spread spectrum modulation is
controlled by an external signal input.
The W159 also includes power management control inputs. By
using these inputs, system logic can stop CPU and/or PCI
clocks or power down the entire device to conserve system
power.
Pin Definitions
Pin Name
Pin
No.
Pin
Type
Pin Description
CPU0:6
48, 47, 44, 43,
40, 39, 36
O
CPU Clock Outputs 0 through 6: These seven CPU clocks run at a frequency set
by SEL133/100#. Output voltage swing is set by the voltage applied to VDDQ2. For
4-way SMP systems that do not require more than 5 CPU outputs, CPU5 and CPU6
can be disabled by asserting 6W/4W# during power-up.
CPUdiv2_ 0:1
32, 31
O
Synchronous Memory Reference Clock Output 0 through 1: Reference clock
for Direct RDRAM clock generators running at 1/2 CPU clock frequency. Output
voltage swing is set by the voltage applied to VDDQ2. For systems using SDRAM,
CPUdiv2_0:1 output can be disabled by tying VDDQ2 on pin 35 to GND.
3V33_0:1
23, 24
O
33-MHz Fixed-Frequency Output: These are fixed-frequency outputs that can be
used to drive PCI devices.
REF0/
FIXAPIC#*
9
I/O
14.318-MHz Reference Clock Output/APIC Speed Select: During normal opera-
tions, this is a 3.3V 14.318-MHz reference output. During power-up, it is sampled
to determine the operating frequency of APIC. If the sample is a “1,” APIC will be
set at CPU/4. If it is a “0,” APIC will be fixed at 16.667 MHz.
REF1/TEST#*
10
I/O
14.318-MHz Reference Clock Output/Test Mode: During normal operations, this
is a 3.3V 14.318-MHz reference output. The input is sampled at power-up to deter-
mine if the device should initialize for normal operations or test mode.
APIC0:6
4, 3, 1, 56, 55
53, 52
O
Synchronous I/OAPIC Clock Outputs: APIC output frequency is determined by
FIXAPIC# strapping. For 4-way SMP systems that do not require more than 5 APIC
outputs, APIC5 and APIC6 can be disabled by asserting 4W/6W# during power up.
48MHz
14
O
48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by
voltage applied to VDDQ3.
3V66_0:3
16, 17, 20, 21
O
66-MHz Output 0 through 3: Fixed 66-MHz outputs.
SEL133/100#
29
I
Frequency Selection Input: 3.3V LVTTL-compatible input that selects CPU output
frequency as shown in Table 1.
X1
6
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
X2
7
O
Crystal Connection: An output connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
6W/4W#*
26
I
4-way/6-way Output Select: This input can be changed after initialization and has
an internal pull-up resistor. If left unconnected during power-up, the outputs are
configured so that all CPU and APIC outputs are active. If it is pulled down during
power-up, CPU5:6 and APIC5:6 will be disabled.
SPREAD#
50
I
Active LOW Spread Spectrum Enable: 3.3V LVTTL-compatible input that enables
spread spectrum mode when held LOW.
PWRDWN#
34
I
Active LOW Power Down Input: 3.3V LVTTL-compatible asynchronous input that
requests the device to enter power down mode.
GND
2, 11, 13, 19,
25, 28, 33, 37,
38, 45, 46, 51
G
Ground Connection
VDDQ3
8, 12, 15, 18,
22, 27
P
Power Connection: Power supply for 3V33, 3V66, 48MHz, and REF output buffers,
core circuitry and PLL circuitry. Connect to 3.3V supply.
VDDQ2
5, 30, 35, 41,
42, 49, 54
P
Power Connection: Power supply for APIC and CPU, CPUdiv2 output buffers.
Connect to 2.5V supply.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
