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U3741BM-M2FL Datasheet(PDF) 10 Page - TEMIC Semiconductors |
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U3741BM-M2FL Datasheet(HTML) 10 Page - TEMIC Semiconductors |
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10 / 25 page  U3741BM Rev. A1, 15-Oct-98 Preliminary Information 10 (25) Bitcheck Mode In bitcheck mode the incoming data stream is examined to distinguish between a valid signal from a correspond- ing transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. Configuring the bitcheck Assuming a modulation scheme that contains 2 edges per bit, two time frame checks are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edge to edge checks respectively. If NBitcheck is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bitcheck takes less time if NBitcheck is set to a lower value. In polling mode, the bitcheck time is not dependent on NBitcheck. Figure 11 shows an example where 3 bits are tested successfully and the data signal is transferred to Pin DATA. According to figure 12, the time window for the bitcheck is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bitcheck limit TLim_min and the upper bitcheck limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds TLim_max, the bitcheck will be terminated and the receiver switches to sleep mode. Dem_out t ee TLim_min TLim_max 1/fSig Figure 12. Valid time window for bitcheck For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A ‘11111...’ or a ‘10101...’ sequence in Manchester or Bi-phase is a good choice concerning that advice. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ± 25% regarding the expected edge-to-edge time tee. Using pre-burst patterns that contain various edge-to- edge time periods, the bitcheck limits must be programmed according to the required span. The bitcheck limits are determined by means of the formula below. TLim_min = Lim_min × TXClk TLim_max = (Lim_max –1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution in defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to the chapter ‘Receiving Mode’. Due to this, the lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. Figures 13, 14 and 15 are illustrating the bitcheck for the default bitcheck limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the ASK/ FSK demodulator (Dem_out) is undefined during that period. When the bitcheck becomes active, the bitcheck counter is clocked with the cycle TXClk. Figure 13 shows how the bitcheck proceeds if the bit- check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In figure 14 the bitcheck fails as the value CV_lim is lower than the limit Lim_min. The bitcheck also fails if CV_Lim reaches Lim_max. This is illustrated in figure 15. Bitcheck Enable IC Dem_out Bitcheck–Counter 0 23 45 6 24 5 17 8 1 36 78 9 11 12 13 14 10 1/2 Bit 15 16 17 18 1 2 3 4 56 ( Lim_min = 14, Lim_max = 24 ) 78 910 11 12 13 14 15 123 4 1/2 Bit 1/2 Bit Bitcheck ok Bitcheck ok T Startup T Clk Figure 13. Timing diagram during bitcheck |
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