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T7906EDD-E Datasheet(PDF) 6 Page - ATMEL Corporation |
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T7906EDD-E Datasheet(HTML) 6 Page - ATMEL Corporation |
6 / 42 page 6 T7906E Rev. A – 27-Aug.-01 cascaded. The timers can also be used to set an external signal when the timeout value is reached. Configuration After a chip reset the T7906E is configured by the internal controller. This can be either by receiving the configuration data from the IEEE-1355 link or by an external controller connected to the host port of the T7906E. Shared I/O Some of the functions of the T7906E presented above share the same I/O pins. This means, that some functions are mutually exclusive. As an example, the GPIO port shares some of its I/O pins with the host interface. If the host interface is not used, these pins are available for GPIO, otherwise they are used as the host address and data bus. The selection of which functions are being used is made by programming the appropri- ate registers after a chip reset. A short overview of the pin allocation and combinations of functions is given in the table below: Note: If the passive FIFO mode is used on the T7906E, the ADC and DAC interfaces can then not be used. JTAG interface For testing purposes a standard IEEE 1149.1 interface is provided. It supports the JTAG functions Bypass, Extest, Sample/Preload, All-Tristate and IDCode. Interface Type Example Mode Interface Type Example Mode 12 3 Host / GPIO2 • • • Timer1 • • • Timer2 • • • UART1 • • • UART2 • • • GPIO0 GPIO7-0 - GPIO7-0 GPIO1 IOB7-0 IOB7-0 FIFO active mode - passive mode RAM - • - ADC • - - DAC • - - |
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