NB100LVEP56

http://onsemi.com

3

D0b

SEL0

X

L

L

H

H

Table 2. TRUTH TABLE

Q0, Q0

a

b

b

a

a

SEL1

X

L

H

H

L

COM_SEL

H

L

L

L

L

Q1, Q1

a

b

a

a

b

17

18

16

15

14

13

12

4

3

56

78

9

11

10

19

20

2

1

NB100LVEP56

Q1

Q1

Q0

18

12

4

3

5

6

78

9

D0b

11

10

D0a

SEL1

2

1

D1a D1a

COM

SEL

17

16

15

14

13

19

24

23

22

20

21

NB100LVEP56

Q0

D0a

D1b

D1b

Exposed Pad

(EP)

D0b

D0b

D1a

Q0

SEL0

SEL1

Q1

Q1

D0a

Q0

D1a

D0a

COM_SEL

D1b

D1b

1

1

Figure 1. Logic Diagram

Figure 2. TSSOP−20 Lead Pinout (Top View)

Figure 3. QFN−24 Lead Pinout (Top View)

Table 3. ATTRIBUTES

Characteristics

Value

Internal Input Pulldown Resistor

(R1)

75 kW

Internal Input Pullup Resistor

(R2)

37 kW

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 2 kV

> 150 V

> 2 kV

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

354 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.