SRAM

MT5C1009

Austin Semiconductor, Inc.

MT5C1009

Rev. 5.5 8/01

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

2

FUNCTIONAL BLOCK DIAGRAM

NOTE: The two least significant row address bits (A8 and A6) are encoded using gray code.

TRUTHTABLE

262,144-BIT

MEMORY ARRAY

GND

DQ8

DQ1

CE\

OE\

WE\

COLUMN DECODER

POWER

DOWN

CE\

WE\

OE\

MODE

I/O PIN

SUPPLY CURRENT

H

X

X

Not Selected

High-Z

X

X

X

Not Selected

High-Z

L

H

H

Output Disable

High-Z

L

H

L

Read

L

L

X

Write