Complete SDARS Receiver

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11

F19 to F16 is the upper-part binary-written main

1,048,576.

BYTES PLLfrac1 and PLLfrac0:

F15 to F0 is the lower-part binary-written main divid-

BYTE Control:

REF = reference division ratio: REF = 0 (/1) and REF

= 1 (/2)

CHP = charge-pump current: CHP = 0 (0.6mA) and

CHP = 1 (1.2mA)

D48 = LO division ratio: D48 = 0 (/4) and D48 = 1 (/8)

SDR = shutdown RF AGC: SDR = 0 (on) and SDR =

1 (shutdown)

ANT = antenna overcurrent protection: ANT = 0 (on)

and ANT = 1 (shutdown)

SDF = shutdown front end: SDF = 0 (on) and SDF =

1 (shutdown)

SDB = shutdown back end: SDB = 0 (on) and SDB =

1 (shutdown)

SDP = shutdown PLL: SDP = 0 (on) and SDP = 1

(shutdown)

BYTE CustomGain:

RF4/RF3/RF2/RF1/RF0 = RF AGC engagement

threshold (dBm): see the RF AGC Settling Time

graph in the Typical Operating Characteristics.

LP1/LP0 = change by 250kHz the LPF corner fre-

quency: LP1/LP0 = 10 (nominal), LP1/LP0 = 11

(decrease), LP1/LP0 = 00 (increase)

HPF = HPF gain increase by 4dB: HPF = 0 (off) and

HPF = 1 (on)

BYTE PMA_Test:

PM3/PM2/PM1/PM0 = PMA gain cutback (dB):

SDX = shutdown reference buffer: SDX = 0 (on) and

SDX = 1 (shutdown)

T2/T1/T0 = test bits: 000 (normal), 001 (main divi-

sion), 010 (reference division), 011 (reserved),

100 (CHP low-Z), 101 (CHP source on), 110 (CHP

sink on), 111 (CHP high-Z)

BYTE LPFTrim:

B4/B3/B2/B2A/B1 = Reserved for LPF trim. All = 0 in

normal operating mode

IOT = LPF corner frequency setup: IOT = 0 (default

IOT = 0 in normal operating mode

BYTE Status:

RF AGC = RF AGC status: RF AGC = 0 (is not

engaged) and RF AGC = 1 (engaged)

ACP = antenna current protection: ACP = 0 (no over-

current) and ACP = 1 (overcurrent)

AND = antenna detection: ANT = 0 (current < thresh-

old) and ANT = 1 (current > threshold)

LD = lock detect: LD = 0 (out of lock) and LD = 1

(lock)

BYTE Reserved:

Inactive at this time, all bits are 0

Register configuration for the LO generation

when the comparison frequency = 23.92MHz:

to generate 2078.893333MHz:

PLLint = 01010110, PLLfrac2 = 00011110,

PLLfrac1= 10010000, PLLfrac0 = 01101001

to generate 2067.777778MHz:

PLLint = 01010110, PLLfrac2 = 00010111,

PLLfrac1 = 00100001, PLLfrac0 = 00000010

to generate 1871.004000 MHz:

PLLint = 01001110, PLLfrac2 = 00010011,

PLLfrac1 = 10000001, PLLfrac0 = 11111000

to generate 1861.000000MHz:

PLLint = 01001101, PLLfrac2 = 00011100,

PLLfrac1 = 11010000, PLLfrac0 = 11101000

READ-FROM MODE

RESET VALUE

ADDRESS (hex)

MSB

CONTROL BYTE

LSB

Address

—

C3

C5

C7

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

1

1

1

0

1

1

1

1

Reserved

00000000

00

0

0

0

0

0

0

0

0

Status

00000000

01

0

0

0

0

RFAGC

ACP

AND

LD

Table 4. MAX2140 Read Programming Bits