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MAX1064AEEG Datasheet(PDF) 4 Page - Maxim Integrated Products

Part # MAX1064AEEG
Description  400ksps, 5V, 8-/4-Channel, 10-Bit ADCs with 2.5V Reference and Parallel Interface
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1064AEEG Datasheet(HTML) 4 Page - Maxim Integrated Products

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Operating mode,
400ksps, +5V, 8-/4-Channel, 10-Bit ADCs
with +2.5V Reference and Parallel Interface
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
CONDITIONS
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
Standby mode
Operating mode,
fSAMPLE = 400ksps
1.0
1.2
mA
2.5
2.9
2.9
3.4
IDD
Positive Supply Current
V
4.5
5.5
VDD
Analog Supply Voltage
200
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +5V ±10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7µF capacitor at REF pin, fCLK = 7.6MHz (50% duty
cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
VLOGIC Current
ILOGIC
CL = 20pF
210
µA
Power-Supply Rejection
PSR
VDD = 5V ±10%, full-scale input
±0.3
±0.9
mV
fSAMPLE = 400ksps
Nonconverting
V
2.7
VDD +
0.3
VLOGIC
Digital Supply Voltage
WR to CLK Fall Setup Time
tCWS
40
ns
ns
CLK Pulse Width High
ns
CLK Period
tCH
40
tCP
132
CLK Pulse Width Low
tCL
40
ns
Data Valid to WR Rise Time
tDS
40
ns
WR Rise to Data Valid Hold Time
tDH
0
ns
CLK Fall to WR Hold Time
tCWH
40
ns
CS to CLK or WR Setup Time
tCSWS
60
ns
CLK or WR to CS Hold Time
tCSWH
0
ns
CS Pulse Width
tCS
100
ns
WR Pulse Width
tWR
60
ns
(Note 8)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Shutdown mode
210
0.5
0.8
POWER REQUIREMENTS
µA
External reference
Internal reference
External reference
Internal reference


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