FLASH MEMORY

43

Preliminary

K9WAG08U1M

K9K8G08U0M

Figure 14. Two-Plane Page Program

80h

11h

Data

Input

Plane 0

(2048 Block)

Block 0

Block 2

Block 4094

Block 4092

80h

R/B

Address & Data Input

11h

81h

10h

70h

Address & Data Input

81h

10h

Plane 1

(2048 Block)

Block 1

Block 3

Block 4095

Block 4093

Figure 15. Two-Plane Block Erase Operation

60h

R/B

60h

D0h

I/O 0

Pass

Fail

Address (3 Cycle)

Address (3 Cycle)

70h

"0"

"1"

:

Fixed ’Low’

:

Fixed ’High’

Two-Plane Block Erase

Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each

plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by

three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.

The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/

Busy status bit (I/O 6).

Two-plane erase operations can be executed by dividing the memory array into plane 0~1 or plane 2~3 separately.

For example, two-plane erase operation into plane 0 and plane 2 is prohibited. That is to say, two-plane erase operation into plane 0

and plane 1 or into plane 2 and plane 3 is allowed.

:

Fixed ’Low’

:

Valid

:

Fixed ’High’

:

:

Valid

:

plane 2 ~3 is same. two-plane page program into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.

NOTE : Two-plane block erase into plane 0&2(or plane 0&3, or plane 1&2, or plane 1&3) is prohibited.

2.Any command between 11h and 81h is prohibited except 70h and FFh.

Note2

: