K4S511633C-YL/N/P

Rev. 1.2 Dec. 2002

CMOS SDRAM

SIMPLIFIED TRUTH TABLE

(V=Valid, X=Don

′t Care, H=Logic High, L=Logic Low)

Notes :

1. OP Code : Operand Code

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are the same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency

is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).

COMMAND

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

Note

Register

Mode Register Set

H

X

L

L

L

L

X

OP CODE

1, 2

Refresh

Auto Refresh

H

H

L

L

L

H

X

X

3

Self

Refresh

Entry

L

3

Exit

L

H

L

H

H

H

X

X

3

H

X

X

X

3

Bank Active & Row Addr.

H

X

L

L

H

H

X

V

Row Address

Read &

Column Address

Auto Precharge Disable

H

X

L

H

L

H

X

V

L

Column

Address

4

Auto Precharge Enable

H

4, 5

Write &

Column Address

Auto Precharge Disable

H

X

L

H

L

L

X

V

L

Column

Address

4

Auto Precharge Enable

H

4, 5

Burst Stop

H

X

L

H

H

L

X

X

6

Precharge

Bank Selection

H

X

L

L

H

L

X

V

L

X

All Banks

X

H

Clock Suspend or

Active Power Down

Entry

H

L

H

X

X

X

X

X

L

V

V

V

Exit

L

H

X

X

X

X

X

Precharge Power Down Mode

Entry

H

L

H

X

X

X

X

X

L

H

H

H

Exit

L

H

H

X

X

X

X

L

V

V

V

DQM

H

X

V

X

7

No Operation Command

H

X

H

X

X

X

X

X

L

H

H

H