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IDT72281L10TFI Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72281L10TFI Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 26 page COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72281/72291 CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9 6 AC ELECTRICAL CHARACTERISTICS(1) (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C) Commercial Commercial & Industrial(2) IDT72281L10 IDT72281L15 IDT72281L20 IDT72291L10 IDT72291L15 IDT72291L20 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency — 100 — 66.7 — 50 MHz tA Data Access Time 2 6.5 2 10 2 12 ns tCLK Clock Cycle Time 10 — 15 — 20 — ns tCLKH Clock High Time 4.5 — 6 — 8 — ns tCLKL Clock Low Time 4.5 — 6 — 8 — ns tDS DataSetupTime 3 — 4 — 5 — ns tDH Data Hold Time 0 — 1 — 1 — ns tENS Enable Setup Time 3 — 4 — 5 — ns tENH Enable Hold Time 0 — 1 — 1 — ns tLDS LoadSetupTime 3 — 4 — 5 — ns tLDH Load Hold Time 0 — 1 — 1 — ns tRS Reset Pulse Width(3) 10 — 15 — 20 — ns tRSS ResetSetupTime 10 — 15 — 20 — ns tRSR Reset Recovery Time 10 — 15 — 20 — ns tRSF Reset to Flag and Output Time — 10 — 15 — 20 ns tFWFT Mode Select Time 0 — 0 — 0 — ns tRTS RetransmitSetupTime 3 — 4 — 5 — ns tOLZ Output Enable to Output in Low Z(4) 0— 0 — 0— ns tOE Output Enable to Output Valid 2 6 3 8 3 10 ns tOHZ Output Enable to Output in High Z(4) 26 3 8 3 10 ns tWFF Write Clock to FF or IR — 6.5 — 10 — 12 ns tREF Read Clock to EF or OR — 6.5 — 10 — 12 ns tPAF Write Clock to PAF — 6.5 — 10 — 12 ns tPAE Read Clock to PAE — 6.5 — 10 — 12 ns tHF Clock to HF —16 — 20 — 22 ns tSKEW1 Skew time between RCLK and WCLK for FF/IR 5— 6 — 10 — ns tSKEW2 Skew time between RCLK and WCLK for PAE and PAF 12 — 15 — 20 — ns tSKEW3 Skew time between RCLK and WCLK for EF/OR 60 — 60 — 60 — ns NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device. 3. Pulse widths less than minimum values are not allowed. 4. Values guaranteed by design, not currently tested. Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V OutputReferenceLevels 1.5V OutputLoad See Figure 2 AC TEST CONDITIONS * Includes jig and scope capacitances. 4675 drw 04 1.1K 30pF* 680 Ω 5V D.U.T. Figure 2. Output Load |
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