3

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72281/72291

CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9

DESCRIPTION (CONTINUED)

Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO

MASTER RESET (

MRS)

READ CLOCK (RCLK)

READ ENABLE (

REN)

OUTPUT ENABLE (

OE)

EMPTY FLAG/OUTPUT READY (

EF/OR)

PROGRAMMABLE ALMOST-EMPTY (

PAE)

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN)

LOAD (

LD)

FULL FLAG/INPUT READY (

FF/IR)

PROGRAMMABLE ALMOST-FULL (

PAF)

IDT

72281

72291

PARTIAL RESET (

PRS)

FIRST WORD FALL THROUGH/SERIAL INPUT

(FWFT/SI)

RETRANSMIT (

RT)

4675 drw 03

HALF-FULL FLAG (

HF)

SERIAL ENABLE(

SEN)

FWFT mode.

HF, PAEand PAF are always available for use, irrespective of

timingmode.

PAEand PAF can be programmed independently to switch at any point in

memory. (See Table I and Table II.) Programmable offsets determine the flag

switching threshold and can be loaded by two methods: parallel or serial. Two

defaultoffsetsettingsarealsoprovided,sothat

PAEcanbesettoswitchat127

or 1,023 locations from the empty boundary and the

PAFthresholdcanbeset

at 127 or 1,023 locations from the full boundary. These choices are made with

the

LD pin during Master Reset.

For serialprogramming,

SENtogetherwithLDoneachrisingedgeofWCLK,

are used to load the offset registers via the Serial Input (SI). For parallel

programming,

WENtogetherwithLDoneachrisingedgeofWCLK,areused

REN together withLD on each rising edge

ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether

serial or parallel offset loading has been selected.

During Master Reset (

MRS)thefollowingeventsoccur:Thereadandwrite

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

Standard mode or FWFT mode. The

LDpinselectseitherapartialflagdefault

setting of 127 with parallel programming or a partial flag default setting of 1,023

with serial programming. The flags are updated according to the timing mode

anddefaultoffsetsselected.

The Partial Reset (

PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, partial flag programming

method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset

remain unchanged. The flags are updated according to the timing mode and

offsets in effect.

PRS is useful for resetting a device in mid-operation, when

reprogramming partial flags would be undesirable.

The Retransmit function allows data to be reread from the FIFO more than

once. A LOW on the

RTinputduringarisingRCLKedgeinitiatesaretransmit

operation by setting the read pointer to the first location of the memory array.

If, at any time, the FIFO is not actively performing an operation, the chip will

automatically power down. Once in the power down state, the standby supply

currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol

inputs) will immediately take the device out of the power down state.

The IDT72281/72291 are fabricated using IDT’s high speed submicron

CMOS technology.