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M38B41EAH-XXXXFP Datasheet(PDF) 3 Page - Mitsubishi Electric Semiconductor |
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M38B41EAH-XXXXFP Datasheet(HTML) 3 Page - Mitsubishi Electric Semiconductor |
3 / 78 page 3 38B4 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PIN DESCRIPTION Table 1 Pin description (1) Pin Name Function VCC, VSS Power source • Apply voltage of 4.0–5.5 V to VCC , and 0 V to VSS. VEE Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, and P3. power source VREF Reference • Reference voltage input pin for A-D converter. voltage AVSS Analog power • Analog power source input pin for A-D converter. source • Connect to VSS. RESET Reset input • Reset input pin for active “L”. XIN Clock input • Input and output pins for the main clock generating circuit. • Feedback resistor is built in between XIN pin and XOUT pin. • Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. • When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. • The clock is used as the oscillating source of system clock. P00/FLD8– I/O port P0 • 8-bit I/O port. • FLD automatic display P07/FLD15 • I/O direction register allows each pin to be individually programmed as either pins input or output. • At reset, this port is set to input mode. • A pull-down resistor is built in between port P0 and the VEE pin. • CMOS compatible input level. • High-breakdown-voltage P-channel open-drain output structure. • At reset, this port is set to VEE level. P10/FLD16– Output port P1 • 8-bit output port. • FLD automatic display P17/FLD23 • A pull-down resistor is built in between port P1 and the VEE pin. pins • High-breakdown-voltage P-channel open-drain output structure. • At reset, this port is set to VEE level. P20/BUZ02/ I/O port P2 • 8-bit I/O port with the same function as port P0. • FLD automatic display FLD0– • Low-voltage input level. pins P27/FLD7 • High-breakdown-voltage P-channel open-drain output structure. • Buzzer output pin (P20) P30/FLD24– Output port P3 • 8-bit output port. • FLD automatic display P37/FLD31 • A pull-down resistor is built in between port P3 and the VEE pin. pins • High-breakdown-voltage P-channel open-drain output structure. • At reset, this port is set to VEE level. P40/INT0, I/O port P4 • 7-bit I/O port with the same function as port P0. • Interrupt input pins P41/INT1, • CMOS compatible input level In the mask option type P, P42/INT3 • N-channel open-drain output structure. INT3 cannot be used. P43/BUZ01 • Buzzer output pin P44/PWM1 • PWM output pin (Timer output pin) P45/T1OUT, • Timer output pin P46/T3OUT P47/INT2 Input port P4 • 1-bit input port. • Interrupt input pin • CMOS compatible input level. Function except a port function XOUT Clock output |
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