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LTM8056 Datasheet(PDF) 17 Page - Linear Technology |
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LTM8056 Datasheet(HTML) 17 Page - Linear Technology |
17 / 28 page LTM8056 17 8056fa For more information www.linear.com/LTM8056 where MODE and LL are tied together, a small capacitor (~0.1µF) from these pins to GND may improve the light load transient response by delaying the transition from the discontinuous to forced continuous switching modes. MODE may be tied to GND for the purpose of blocking reverse current if no output current sense resistor is used. FB Resistor Divider and Load Regulation The LTM8056 regulates its FB pin to 1.2V, using a resistor divider to sense the output voltage. The location at which the output voltage is sensed affects the load regulation. If there is a current sense resistor between VOUT and IOUT, and the output is sensed at VOUT, the voltage at the load will drop by the value of the current sense resistor multiplied by the output current. If the output voltage can be sensed at IOUT, the load regulation may be improved. PCB Layout Most of the headaches associated with PCB layout have been alleviated or even eliminated by the high level of integration of the LTM8056. The LTM8056 is neverthe- less a switching power supply, and care must be taken to minimize EMI and ensure proper operation. Even with the high level of integration, you may fail to achieve specified operation with a haphazard or poor layout. See Figure 6 for a suggested layout. Ensure that the grounding and heat sinking are acceptable. A few rules to keep in mind are: 1. Place the RFB and RT resistors as close as possible to their respective pins. 2. Place the CIN capacitor as close as possible to the VIN and GND connection of the LTM8056. 3. Place the COUT capacitor as close as possible to the VOUT and GND connection of the LTM8056. 4. Minimize the trace resistance between the optional outputcurrentsenseresistor,ROUT,andVOUT. Minimize the loop area of the IOUT trace and the trace from VOUT to ROUT. 5. Minimizethetraceresistancebetweentheoptionalinput current sense resistor (RIN) and VIN. Minimize the loop area of the IIN trace and the trace from VIN to RIN. 6. Place the CIN and COUT capacitors such that their ground current flow directly adjacent or underneath the LTM8056. 7. Connect all of the GND connections to as large a copper pour or plane area as possible on the top layer. Avoid breaking the ground connection between the external components and the LTM8056. 8. Use vias to connect the GND copper area to the board’s internal ground planes. Liberally distribute these GND vias to provide both a good ground connection and thermal path to the internal planes of the printed circuit board. Pay attention to the location and density of the thermal vias in Figure 6. The LTM8056 can benefit from the heat sinking afforded by vias that connect to internal GND planes at these locations, due to their proximity to internal power handling components. The optimum number of thermal vias depends upon the printed circuit board design. For example, a board might use very small via holes. It should employ more thermal vias than a board that uses larger holes. Hot-Plugging Safely The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of the LTM8056. However, these capaci- tors can cause problems if the LTM8056 is plugged into a live supply (see Linear Technology Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the volt- age at the VIN pin of the LTM8056 can ring to more than twice the nominal input voltage, possibly exceeding the LTM8056’sratinganddamagingthepart.Iftheinputsupply APPLICATIONS INFORMATION |
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Similar Description - LTM8056 |
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