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LTM4676A Datasheet(PDF) 33 Page - Linear Technology

Part # LTM4676A
Description  Dual 13A or Single 26A 關Module Regulator with Digital Power System Management
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTM4676A Datasheet(HTML) 33 Page - Linear Technology

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LTM4676A
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For more information www.linear.com/LTM4676A
operaTion
sensor, whose temperature readback data and peak value
are available over I2C (READ_TEMPERATURE_11, MFR_
READ_TEMPERATURE_1_PEAK1).Implementationofthe
aforementioned is as follows: (1) local to the LTM4676A,
electrically connect a 10nF X7R capacitor directly from
TSNS1a to SGND; (2) differentially route a pair of traces
from the LTM4676A's TSNS1a and SGND pins to the tar-
get PNP transistor; (3) electrically connect the emitter of
the PNP transistor to TSNS1a; (4) electrically connect the
collector and base of the PNP transistor to SGND.
Powerstagedutycyclereadbacktelemetryisavailableover
I2C (READ_DUTY_CYCLEn registers). Computed channel
input current readback is computed by the LTM4676A as:
MFR_READ_IINn = READ_DUTY_CYCLEn • READ_IOUTn
+ MFR_IIN_OFFSETn
Computed module input current readback is computed
by the LTM4676A as:
READ_IIN=MFR_READ_IIN0 +MFR_READ_IIN1
where MFR_IIN_OFFSETn is a register value representing
the SVIN input bias current. The SVIN current is not dig-
itized by the module. The factory NVM-default value of
MFR_IIN_OFFSETn is 30.5mA, representing the contribu-
tion of current drawn by each of the module’s channels
on the SVIN pin, when the power stages are operating in
forced continuous mode at the factory-default switching
frequency of 500kHz. See Table 8 in the Applications In-
formation section for recommended MFR_IIN_OFFSETn
setting vs Switching Frequency. The aforementioned
method by which input current is calculated yields an ac-
curate current readback value even at light load currents,
but only as long as the module is configured for forced
continuous operation (NVM-factory default). SVIN and
peak SVIN readback telemetry is accessible via I2C in the
READ_VIN and MFR_VIN_PEAK registers, respectively.
The power stage switch nodes are brought out on the SWn
pin for functional operation monitoring and for optional
installation of a resistor-capacitor snubber circuit (termi-
nated to GND) for reduced EMI. Internal 2.2nF snubber
capacitors connected directly to the switch nodes further
facilitate implementation of a snubber network, if desired.
See the Application Information section for details.
The LTM4676A features a write protect (WP) pin. If WP is
opencircuitorlogichigh,I2Cwritesareseverelyrestricted:
onlyI2CwritestothePAGE,OPERATION,CLEAR_FAULTS,
MFR_CLEAR_PEAKS, and MFR_EE_UNLOCK commands
are supported, with the exception that individual fault bits
can be cleared by writing a “1b” to the respective bits in the
STATUS_* registers. Register reads are never restricted.
Not to be confused with the WP pin, the LTM4676A fea-
tures a WRITE_PROTECT register, which is also used to
restrict I2C writes to register contents. Refer to Appendix
C: PMBus Command Details for details. The WP pin and
theWRITE_PROTECTregisterprovidealevelofprotection
againstaccidentalchangestoRAMandEEPROMcontents.
TheLTM4676Asupportsallpossible7-bitslaveaddresses.
The factory NVM-default slave address is 0x4F. The lower
four bits of the LTM4676A’s slave address can be altered
from this default value by connecting a resistor from
the ASEL pin to SGND. See Table 5 in the Applications
Information section for details. Bits[6:4] can be altered by
writing to the SLAVE_ADDRESS command. The value of
the SLAVE_ADDRESS command can be stored to NVM,
however, the lower four bits of the SLAVE_ADDRESS is
always dictated by the ASEL resistor pin-strap setting.
Up to four LTM4676A modules (8 channels) can be par-
alleled, suitable for powering ~100A loads such as CPUs
and GPUs. (See Figure 39) The LTM4676A can be paral-
leled with LTM4620A or LTM4630 modules, as well (see
Figure 40and Figure 41).
EEPROM
The LTM4676A’s control IC contains an internal EEPROM
(non-volatile memory, NVM) with Error Correction Coding
(ECC) tostoreconfigurationsettingsandfaultloginforma-
tion. EEPROM endurance retention and mass write opera-
tion time are specified in the Electrical Characteristics and
Absolute Maximum Ratings sections. Write operations at
TJ < 0°C or at TJ > 85°C are possible although the Electri-
cal Characteristics are not guaranteed and the EEPROM
retention characteristics may be degraded. Read opera-
tions performed at junction temperatures between –40°C
and 125°C do not degrade the EEPROM. The fault logging
function, which is useful in debugging system problems


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