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DS21554LN Datasheet(PDF) 8 Page - Maxim Integrated Products |
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DS21554LN Datasheet(HTML) 8 Page - Maxim Integrated Products |
8 / 124 page DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 8 of 124 1.2. Document Revision History REVISION DESCRIPTION 012799 Initial release 012899 Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz timing 020399 Corrected definition and label of TUDR bit in the THIR register. 021199 Corrected address of IBO register in text. 040199 Added Receive Monitor Mode section 041599 Added section on Protected Interfaces 050799 Corrected pin number and description of FMS in JTAG section 072999 Added list of tables and figures 091499 Added 10 mF cap to interface examples 092399 Corrected definition of DS in pin description. 072401 Typo corrected in JTAG Test Access Port Pins. 021004 Added note to the Receive Information Register, FAS Resync Criteria Met. Corrected Figures 20-1, 20-2, 20-3 with respect to CS. Corrected typo in Figure 18-14 (RCR1.1 reference corrected). Corrected formatting issues. |
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