CY62138CV25/30/33 MoBL®
CY62138CV MoBL®
Document #: 38-05200 Rev. *D
Page 5 of 12
Parameters
2.5V
3.0V
3.3V
Unit
R1
16600
1105
1216
Ω
R2
15400
1550
1374
Ω
RTH
8000
645
645
Ω
VTH
1.20
1.75
1.75
V
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.[5]
Max.
Unit
VDR
VCC for Data Retention
1.5
VCC(max.)
V
ICCDR
Data Retention Current
VCC = 1.5V
CE1 > VCC – 0.2V or CE2 < 0.2V
VIN > VCC − 0.2V or VIN < 0.2V
1
6
µA
tCDR
[6]
Chip Deselect to Data
Retention Time
0
ns
tR
[7]
Operation Recovery Time
tRC
ns
Data Retention Waveform
Switching Characteristics Over the Operating Range[8]
Parameter
Description
55 ns
70 ns
Unit
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
55
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
10
10
ns
tACE
CE1 LOW and CE2 HIGH to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low-Z[9]
5
5
ns
tHZOE
OE HIGH to High-Z[9, 10]
20
25
ns
tLZCE
CE1 LOW and CE2 HIGH to Low-Z
[9]
10
10
ns
tHZCE
CE1 HIGH or CE2 LOW to High-Z
[9, 10]
20
25
ns
tPU
CE1 LOW and CE2 HIGH to Power-up
0
0
ns
tPD
CE1 HIGH or CE2 LOW to Power-down
55
70
ns
Write Cycle[11]
tWC
Write Cycle Time
55
70
ns
tSCE
CE1 LOW and CE2 HIGH to Write End
45
60
ns
Notes:
7.
Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
9.
At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
VCC(min.)
VCC(min.)
tCDR
VDR > 1.5 V
DATA RETENTION MODE
tR
CE1
VCC
CE2
or
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
