CY28347
Document #: 38-07352 Rev. *C
Page 7 of 22
Table 8. Dial-A-Ratio™ AGP(0:2)
DARAG (1:0)
CU/AGP Ratio
00
Frequency Selection Default
01
2/1
10
2.5/1
11
3/1
Byte 5: DDR Clock Register
Bit
@Pup
Pin#
Name
Description
7
0
45
BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V.
6
1
46
FBOUT
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
5
1
29,30
DDRT/C5
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
4
1
31,32
DDRT/C4
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
3
1
35,36
DDRT/C3
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
2
1
37,38
DDRT/C2
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1
1
41,42
DDRT/C1
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
0
1
43,44
DDRT/C0
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
Byte 6: Reserve Register
Bit
@Pup
Description
71
Reserved.
60
Reserved.
50
Reserved.
40
Reserved.
30
Reserved.
20
Reserved.
10
Reserved.
00
Reserved.
Byte 7: Dial-a-Frequency Control Register N
Bit
@Pup
Name
Description
7
0
Reserved
Reserved for device function test.
6
0
N6, MSB
These bits are for programming the PLL’s internal N register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that
are generated from the same PLL, such as PCI) remain at their
existing ratios relative to the CPU clock.
50
N5
40
N4
30
N3
20
N2
10
N1
00
N0, LSB
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