CY2277A
Document #: 38-07332 Rev. *A
Page 2 of 19
Pin Summary
Name
Pins
Description
VDDQ3
7, 15, 21, 28, 34
3.3V Digital voltage supply
VDDQ2
46
IOAPIC Digital voltage supply, 2.5V
VDDCPU
40
CPU Digital voltage supply, 2.5V or 3.3V
AVDD
25, 48
3.3V Analog voltage supply
VSS
3, 10, 17, 24, 31, 37, 43
Ground
XTALIN[2]
4
Reference crystal input
XTALOUT[2]
5
Reference crystal feedback
MODE
6
Mode select input, enables power management features
SEL
18
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SDATA
19
SMBus serial data input for serial configuration port
SCLK
20
SMBus serial clock input for serial configuration port
PWR_DWN
44
Active low control input to put osc., PLLs, and outputs in power down state
PWR_SEL
47
Power select input, indicates whether VDDCPU is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to VDD)
SDRAM7/PCI_STOP
26
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM6/CPU_STOP
27
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM[0:5]
36, 35, 33, 32, 30, 29
SDRAM clock outputs, have same frequency as CPU clocks
CPUCLK[0:3]
42, 41, 39, 38
CPU clock outputs
PCICLK[0:5]
9, 11, 12, 13, 14, 16
PCI clock outputs
PCICLK_F
8
PCI clock output, free-running
IOAPIC
45
IOAPIC clock output
REF[0:1]
1, 2
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USBCLK/IOCLK
22, 23
USB or IO clock outputs, frequency selected by serial word
Note:
2.
For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF.
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