CY25200
Document #: 38-07633 Rev. *A
Page 4 of 11
The CLKSEL control pin enables the user to change the output
frequency from one frequency (e.g., frequency A) to another
frequency (e.g., frequency B). These must be related
frequencies that can be derived off of a common VCO
frequency, e.g., 33.333 MHz and 66.666 MHz can both be
derived from a VCO = 400 MHz and dividing it down by 12 and
6 respectively. Table 3 shows an example of how this can be
implemented. The VCO frequency range is 100–400MHz. The
CY25200 has two separate dividers, Divider 1 and Divider 2,
these two can be loaded to have any number between 2 and
130 providing two different but related frequencies as
explained above.
In the above example SSCLK5 (pin 14) and SSCLK6(pin 15)
are used as output clocks, however they could have been
used as control signals. See Figure 2 for the pinout.
Input Frequency (XIN, pin 1 and XOUT, pin 16)
The input to the CY25200 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock sig-
nal is 8 to 166 MHz.
CXIN and CXOUT (pin 1 and pin 16)
The load capacitors at pin 1 (CXIN) and pin 16 (CXOUT) can be
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of CXIN and CXOUT for matching crystal
load (CL) can be calculated using the following formula:
CXIN = CXOUT = 2CL – CP
Where CL is the crystal load capacitor as specified by the crys-
tal manufacturer and CP is the parasitic PCB capacitance.
For example, if a fundamental 16-MHz crystal with CL of 16 pF
is used and CP is 2 pF, CXIN and CXOUT can be calculated as:
CXIN = CXOUT = (2 x 16) – 2 = 30 pF.
If using a driven reference clock, set CXIN and CXOUT to the
minimum value 12 pF.
Output Frequency (SSCLK1 through SSCLK6 Outputs)
All of the SSCLK outputs are produced by synthesizing the
input reference frequency using a PLL and modulating the
VCO frequency. SSCLK[1:4] can be programmed to be only
output clocks (SSCLK). SSCLK5 and SSCLK6 can also be
programmed to function the same as SSCLK[1:4] or a buffered
copy of the input reference (REFOUT) or they can be
programmed to be a control pin as discussed in the control
pins section. To utilize the 2.5V output drive option on
SSCLK[1:4], VDDL must be connected to a 2.5V power supply
(SSCLK[1:4] outputs are powered by VDDL). When using the
2.5V output drive option, the maximum output frequency on
SSCLK[1:4] is 166MHz.
Spread Percentage (SSCLK1 through SSCLK6 Outputs)
The SSCLK frequency can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
Frequency Modulation
The frequency modulation is programmed at 31.5 kHz for all
SSCLK frequencies from 3 to 200 MHz. Contact the factory if
a higher modulation frequency is required.
Table 3. Using Clock Select, CLKSEL Control Pin
Input Freq.
(MHz)
CLKSEL
(Pin 4)
SSCLK1
(Pin 7)
SSCLK2
(Pin 8)
SSCLK3
(Pin 9)
SSCLK4
(Pin 12)
REFOUT
(Pin 14)
REFOUT
(Pin 15)
14.318
CLKSEL = 0
33.33
33.33
33.33
33.33
14.318
14.318
CLKSEL = 1
66.66
66.66
66.66
66.66
14.318
14.318
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
SSON
33.33/66.66MHz
14.318MHz
XOUT
VDD
CLKSEL
AVSS
33.33/66.66MHz
REFOUT(14.318MHz)
REFOUT(14.318MHz)
AVDD
VDDL
33.33/66.66MHz
33.33/66.66MHz
Figure 2. Table 3 Configuration Pinout
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