10 / 33 page  CY7C1355B CY7C1357B Document #: 38-05117 Rev. *B Page 10 of 33 OE 86 F4 B8 Input- Asynchronous Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the de- vice to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deas- serted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. CEN 87 M4 A7 Input- Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deas- serted HIGH the Clock signal is masked. Since deassert- ing CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ 64 T7 H11 Input- Asynchronous ZZ “Sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs 58,59,62,63, 68,69,72,73, 8,9,12,13, 18,19,22,23 P7,K7,G7, E7,F6,H6, L6,N6,D1, H1,L1,N1, E2,G2,K2, M2 J10,K10, L10,M10, D11,E11, F11,G11,J1, K1,L1,M1, D2,E2,F2, G2 I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle. The di- rection of the pins is controlled by OE. When OE is assert- ed LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition.The outputs are automatically three-stated during the data por- tion of a Write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQP[A:B] 74,24 D6,P2 C11,N1 I/O- Synchronous Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During Write sequences, DQP[A:B] is controlled by BW[A:B] correspondingly. MODE 31 R3 R1 Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. VDD 15,41,65,91 C4,J2,J4, J6,R4 D4,D8,E4, E8,F4,F8, G4,G8,H2, H4,H8,J4, J8,K4,K8, L4,L8,M4, M8 Power Supply Power supply inputs to the core of the device. VDDQ 4,11,20,27, 54,61,70,77 A1,A7,F1, F7,J1,J7, M1,M7,U1 ,U7 C3,C9,D3, D9,E3,E9, F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 I/O Power Supply Power supply for the I/O circuitry. CY7C1357B–Pin Definitions (continued) Name TQFP BGA fBGA I/O Description |
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