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CY2CC1810 Datasheet(PDF) 4 Page - Cypress Semiconductor

Part # CY2CC1810
Description  1:10 Clock Fanout Buffer with Output Enable
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2CC1810 Datasheet(HTML) 4 Page - Cypress Semiconductor

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COMLINK™ SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 4 of 8
Parameter Measurement Information: VDD @ 2.5V
[3,5,6]
Notes:
3.
CL includes probe and jig capacitance.
4.
Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with
internal conditions such that the output is HIGH except when disabled by the output control.
5.
All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50
Ω, t
R < 2.5 nS, tF < 2.5 nS.
6.
Outputs are measured one at a time with one transition per measurement.
7.
tPLZ and tPHZ are the same as tDIS.
8.
tPZL and tPZH are the same as tEN.
9.
tPLH and tPHL are the same as tPD.
AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, TA = –40°C to +85°C (See Figure 1)
Parameter
Description
Min.
Typ.
Max. Unit
tPLH
Propagation Delay – Low to High
See Figure 4
1.5
3.8
3.5
nS
tPHL
Propagation Delay – High to Low
1.5
3.8
3.5
nS
tPHZ
Propagation Delay – High to High Z
See Figure 5
5nS
tPLZ
Propagation Delay – Low to High Z
4
nS
tR
Output Rise Time
See Figure 4
0.4
V/nS
tF
Output Fall Time
0.6
V/nS
tSK(0)
Output Skew: Skew between outputs of the same package (in phase) See Figure 12
0.2
nS
tSK(p)
Pulse Skew: Skew between opposite transitions of the same output
(tPHL – tPLH)
See Figure 11
0.2
nS
tSK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
See Figure 13
0.3
nS
tOFF
Delay from OE to Driver Off
5.0
nS
tON
Delay from OE to Driver on
5.0
nS
From O utput
Under Test
C
L = 5 0 pF
500 ohm
V
SS
Open
2x VDD
500 ohm
Figure 1. Load Circuit
2.5 V
0 V
Input
t
w(20-80)
2.5 V
0 V
1.25 V
1.25 V
Input
t
w(50-50)
1.25 V
Figure 2. Voltage Waveforms–Pulse Duration
From Output
Under Test
C
L = 3 pF
500 ohm
Figure 3. Point-to-Point Load Circuit
Table 1.
Test
S1
tPLH/tPHL
Open
See Figure 4
tPLZ/tPZL
2 × VDD
See Figure 5
tPHZ/tPZH
VSS
1.25 V
1.25 V
1.25 V
1.25 V
t
PLH
t
PHL
2.5 V
V
OH
V
OL
0 V
Input
Output
Figure 4. Voltage Waveforms–Propagation Delay Times[9]
Output Control
(low-level enabling)
Waveform 1
S1 at 2 x VDD
2.5 V
Waveform 2
S1 at GND
2.5 V
t
PLZ
t
PHZ
t
PZH
t
PZL
1.25 V
1.25V
0 V
~0 V
V
OL + 0.3V
V
OH- 0.3V
V
OL
V
OH
Z
Z
1.25 V
VOH (min)
VOL
(max)
Figure 5. Voltage Waveforms–
Enable and Disable Times[4,7,8]


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