3

AT24C02A/04A/08A/16A

5083A–SEEPR–9/04

The AT24C08A only uses the A2 input for hardwire addressing, and a total of two 8K

devices may be addressed on a single bus system. The A0 and A1 pins are no-

connects.

The AT24C16A does not use the device address pins, which limits the number of

devices on a single bus to one. The A0, A1, and A2 pins are no-connects.

WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a WP pin that provides

hardware data protection. The WP pin allows normal read/write operations when con-

feature is enabled and operates as shown. (See Table 1.

)

Table 1. Write Protect

bytes each. Random word addressing requires an 8-bit data word address.

AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16

bytes each. Random word addressing requires a 9-bit data word address.

AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16

bytes each. Random word addressing requires a 10-bit data word address.

AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of

16 bytes each. Random word addressing requires an 11-bit data word address.

Note:

This parameter is characterized and is not 100% tested.

WP Pin Status

Part of the Array Protected

24C02A

24C04A

24C08A

24C16A

Upper Half

(1K) Array

Upper Half

(2K) Array

Full (8K)

Array

Full (16K)

Array

At GND

Normal Read/Write Operations

Table 2. Pin Capacitance

Symbol

Test Condition

Max

Units

Conditions

Input/Output Capacitance (SDA)

8

pF

6

pF