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ST2202 Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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ST2202 Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
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3 / 65 page  Sitronix ST2202 Ver 2.0a 3/65 2003-May-05 3 3.. S SIIG GN NA AL L D DE ES SC CR RIIP PT TIIO ON NS S TABLE 3-1 Signal Function Groups Function Group Pad No. Designation Description Power 17, 52, 90 VCC , PVCC VCC: Power supply for system PVCC: Power supply for PSGO and PSGOB Ground 22, 48, 49, 71 GND , PGND GND: System power ground PGND: Power ground for PSGO and PSGOB System control 15, 1, 77, 26 RESET , TEST1/2 MMD/ CS0 RESET : Active low system reset signal input TEST1/2: Leave them open when normal operation MMD/CS0: Memory modes selection pin Normal mode: Enable internal ROM. MMD/ CS0 connects to GND. Emulation mode: Disable internal ROM. MMD/ CS0 connects to chip-select pin of external ROM. One resistor should be added between VCC and this pin. After reset cycles, MMD/ CS0 changes to be an output, and outputs signal CS0 . Clock 16, 18~21 OSCXO, OSCXI, OSCI, XIO, XMD XMD: High frequency oscillator (OSC) mode selection input Low: Crystal mode. One crystal or resonator should be connected between OSCI and XIO High: Resistor oscillator mode. One resistor should be connected between OSCI and VCC OSCXI, OSCXO: Connect one 32768Hz crystal between these two pins when using low frequency oscillator 69, 70 WR , RD External memory R/W control signals 2~4, 81~89, 91~101 A[22:0] External memory address bus External memory bus signals 72~76, 78~80 D[7:0] External memory data bus PSG/PWM DAC 50, 51 PSGO, PSGOB PSG outputs. Connect to one buzzer or speaker Keyboard scan signal (return line) 23~25, 27~31 PA7~0 I/O port A GPIO 32~39 PB7~0 I/O port B Chip selects 61~66 CS6 /A23/PD5 , 1 ~ CS5 /PD4~0 I/O port D and chip-select outputs UART 46, 47, 67, 68 RXD0/PC7 , TXD0/PC6 , RXD1/PD7 , TXD1/PD6 UART signals and I/Os SPI 41~45 DATA_READY /PC5 , SS /PC4 , SDO/PC3 , SDI/PC2 , SCK/PC1 SPI signals and I/Os |
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