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SN74GTLP2033 Datasheet(PDF) 2 Page - Texas Instruments

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Part No. SN74GTLP2033
Description  8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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SN74GTLP2033
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER
WITH SPLIT LVTTL PORT AND FEEDBACK PATH
SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP2033 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V
and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and can be directly driven by TTL or 5-V CMOS devices. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OEAB should be tied to VCC through a pullup resistor
and OEAB and OEBA should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sinking/current-sourcing capability of the driver.
terminal assignments
1234
5
6
A
IMODE1
NC
NC
NC
NC
IMODE0
B
AO1
AI1
GND
GND
BIAS VCC
B1
C
AO2
AI2
VCC
ERC
OEAB
B2
D
AO3
AI3
GND
GND
OEAB
B3
E
AO4
AI4
CLKAB/LEAB
B4
F
AO5
AI5
CLKBA/LEBA
B5
G
AO6
AI6
GND
GND
OEBA
B6
H
AO7
AI7
VCC
VCC
LOOPBACK
B7
J
AO8
AI8
GND
GND
VREF
B8
K
OMODE0
NC
NC
NC
NC
OMODE1
NC = No internal connection
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1
2
3456




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