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75P42100 Datasheet(PDF) 1 Page - Integrated Device Technology |
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75P42100 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 3 page JUNE 2003 DSC-5346/02 1 © 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. NETWORK SEARCH ENGINE 32K x 72 Entries Datasheet Brief 75P42100 Device Description IDT provides proven, industry-leading network search engines (NSEs)andacomprehensivesuiteofsoftwarethatenableandaccelerate the intelligent processing of network services in communications equip- ment.AsapartofthecompleteIDTclassificationsubsystemthatincludes content inspection engines, the IDT family of NSEs delivers high- performance, feature-rich, easy-to-use, integrated search accelerators. TheIDT 75P42100NSEisahighperformancepipelinedlow-power, synchronous full-ternary 32K x 72 entry device. Each entry location in the NSE has both a Data entry and an associated Mask entry. The NSE devices integrate content addressable memory (CAM) technology with high-performancelogic. ThedevicecanperformLookupandLearnNSE operations plus Read, Write, Burst Write, and Dual Write maintenance operations. The IDT 75P42100 NSE device has a bi-directional bus that is a multiplexed address and data bus that can support 100 million sustained searches per second. This device provides array segments which can be configured to enable multiple width lookups from 36 to 576 bits wide. The IDT 75P42100 requires a 1.8-volt VDD supply, a user selectable 1.8 or 2.5-volt VDDQ supply, and a 2.5-volt VBIAS supply. This NSE device provides the user with flexibility and control in determining the device power. Only the array segments that will be used for a specific NSE operation are powered up while the unused segments are not. The IDT 75P42100 NSE utilizes the latest high-performance 1.8V CMOS processing technology and is packaged in a JEDEC Standard, thermally enhanced, low profile Ball Grid Array. The options include a 304 BGA, satisfying smaller footprint requirements and a 372 BGA package that is compatible with the IDT 64K x 72 Entry (75P52100) and 128K x 72 Entry (75K62100) NSE devices. To request the full IDT75P42100 datasheet, please contact your local IDT Sales Representative or call 1-831-754-4555 5346 drw02 Optional Figure 1.0 ASIC / Compatible NSE / SRAM configuration ASIC or FPGA ZBT or Sync SRAM IDT75P42100 or 75P52100 or 75K62100 Network Search Engine Configuration Registers and Ram Control Circuits CLOCK CCLK ÷2 PHASE SRAM CONTROL P R I O R I T Y E N C O D E R S I Z E L O G I C D E C O D E Address MMOUT MATCHOUT REQSTB R/W 534 6 d rw 01 RESET Command Bus Request Data Bus Index Bus Counter BURST NSE REQUEST BUS NSE RESPONSE BUS LAST NSE LAST SRAM ASIC FEEDBACK Bypass DATA ARRAY Comparand Registers Instruction Global Mask Registers Result Register Block Diagram System Configurations The IDT NSEs are designed to fulfill the needs of various types of networking systems. In solutions requiring data searching such as routers, a system configuration as shown in Figure 1.0 may be realized. Maximum flexibility is provided by allowing one board design to be populatedtodayusingeithertheIDT75P42100or75P52100NSEsand later upgraded to use IDT’s 75K62100 NSE. Applications note AN-279 discusseshowtoaccommodateoneboarddesignforanyoftheseNSEs. In this compatible configuration, the NSE interfaces directly to an ASIC/ FPGA for lookups and routes an Index to an associated SRAM device, which supplies the next hop address via an SRAM Data Bus to the ASIC. The NSE provides the required control signals to directly hookuptoZBT™orSynchronousPipelineBurstSRAM. Lookupresults canalsobefeddirectlybacktotheASIC/FPGAwithouttheuseofexternal SRAM. Control of the associated handshake signals is provided by all NSEs to adapt to either configuration. |
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