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Network Search Engine 32K x 72 Entries

Datasheet Brief 75P42100

SRAM Interface

The NSE provides all required address and control signals for a

glueless SRAM interface. The NSE provides a pipelined bypass path for

reads or writes to the external SRAM. The ASIC/FPGA handles the

pipelining of the data to and from the SRAM.

Registers

There are four basic types of registers supported:

segmentation of the entries, timing of outputs and the SRAM interface.

instructions by masking individual bits during a search.

search from a Lookup or Learn operation.

Synchronous Burst Write

The burst write feature has no limit on the number of continuous write

accesses and supports initialization of the NSE.

Width Segmentation Capability

TheNSEsarecapableofperforminglookupsforcomparisonsondata

structures of 72 bits, 144 bits, 288 bits and 576 bits. These devices has

can be configured to meet various system requirements.

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Single Width Array

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Multiple Width Arrays within a Single Device

Multi Match

The Multi-Match feature signals to the user that more than one match

has resulted. The result of the lookup, which defines the highest priority

match, is sent along with the Multi-Match signal.

Power Savings and Classification Features

See the full IDT75P42100 Datasheet for more information.

Functional Highlights

Figure 1.1

Bus Interface

The NSE utilizes a dual bus interface consisting of the NSE Request

Bus and the NSE Response Bus.

The NSE Request Bus is comprised of the Command Bus and the

RequestDataBus. TheCommandBushandlestheinstructiontotheNSE

while the Request Data Bus is the main data path to the NSE.

The72bitbi-directionalRequestDataBusfunctionsasamultiplexed

address and data bus, which performs the writing and reading of NSE

entries, as well as presenting lookup data to the device.

The NSE Response Bus is comprised of an independent unidirec-

tional Index Bus which drives the result of the lookup (or index) to either

an SRAM device or an ASIC. In addition to driving the Index, the NSE

ResponseBusalsodrivestheassociatedSRAMcontrolsignals(

CE/OE,

and

WE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices.

Command Bus

TheCommandBusloadsthe specificinstructionsintotheNSE.These

include:

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Read or Write

A Read or Write instruction operates on a specified data entry, mask

entry, or register.

Data and Mask Array

The NSE has Data cell entries and associ-

atedMaskcellentriesasshowninFig.1.1. This

combination of Data and Mask cell entries en-

ables the NSE to store 0, 1 or X, making it a full

ternary Network Search Engine. During a

lookup operation, both arrays are used along

with a Global Mask Register to find a match to a

requested data word.

A 5346 drw 03

Dat a

Mask

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SRAM No Wait Read

AnSRAMNoWaitReadisaReadinstructiontoanexternalSRAMthat

canbepipelinedwithinaseriesofoperationsanddoesnotrequiretheuser

to wait for the Read to complete before loading the next instruction.

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Dual Write

In addition to individual writes, the NSE has the ability to perform

simultaneous writes to a Data entry and a respective external SRAM

location.

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Lookup

A lookup can be requested in 72-bit, 144-bit, 288-bit or 576-bit widths.

A36-bitlookupcanbeaccomplishedbyusingtwoGlobalMaskRegisters.

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Learn

The NSE implements a fully autonomous Learn Instruction, which

provides a mechanism for the user to write a lookup entry into an unused

locationintheNSEandtheassociateddatainexternalSRAM. Thisallows

the user to update an entry into the NSE which had not previously been

stored. The Learn writes the new entry, making it available for future

lookups.

Features

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Full Ternary 32K x 72 bit content addressable memory

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Upgradeable to 64K x 72 and 128K x 72 NSEs

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Power Management

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Global Mask Registers

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Segments individually configurable

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36/72/144/288/576 multiple width lookups

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100M sustained lookups per second at 72 and 144 width lookups

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Burst write for high speed table updates

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Multi-match

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Learn new entries

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Dual bus interface

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Cascadable to 8 devices with no glue logic or latency penalty

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Glueless interface to standard ZBT™ or

Synchronous Pipelined Burst SRAMs

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Boundary Scan JTAG Interface (IEEE 1149.1compliant)

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1.8V core power supply

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User selectable 2.5V or 1.8V I/O supply