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A8450KLB Datasheet(PDF) 9 Page - Allegro MicroSystems |
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A8450KLB Datasheet(HTML) 9 Page - Allegro MicroSystems |
9 / 15 page 9 A8450KLB-DS, Rev. 1 Worcester, Massachusetts 01615-0036 (508) 853-5000 115 Northeast Cutoff, Box 15036 www.allegromicro.com Allegro MicroSystems, Inc. A8450 Automotive Multioutput Voltage Regulator ENBAT is an edge-triggered enable (logic 1 ≥ 2.7 V), which is used to enable the A8450 in response to a high-voltage signal, such as from an automobile ignition or battery switch. In this capacity, ENBAT is used only as a momentary switch to wake up the device. If there is no need for a high-voltage signal, ENBAT can be pulled low continuously. ENB is used to initiate the reset of the device. If ENBAT is pulled low, ENB acts as a single reset control. Diagnostics. An open drain output, through the NFAULT pin, is pulled low to signal to a DSP or microcontroller any of the following fault conditions: • V5A, the 5 V analog regulator output, is shorted to supply • Either or both of the V5A and the V5D regulator outputs are below their UVLO threshold, VUVLOV5 • Device junction temperature, TJ, exceeds the Thermal Warning threshold, TJTW Charge Pump. The charge pump generates a voltage above VBB in order to provide adequate gate drive for the N-channel buck switch.A0.1 µF ceramic monolithic capacitor, C7, should be connected between the VCP pin and the VBB pin, to act as a reservoir to run the buck converter switching regulator. VCP is internally monitored to ensure that the charge pump is disabled in the case of a fault condition. In addition, a 0.1 µF ceramic monolithic capacitor, C8, should be connected between CP1 and CP2. Power On Reset Delay. The POR block monitors the sup- ply voltages and provides a signal that can be used to reset a DSP or microcontroller. A POR event is triggered by any of the following conditions: • Either V33 or VADJ is pulled below its UVLO threshold, VUVLOV33 or VUVLOVADJ. This occurs if the current limit on either regulator, VOC, is exceeded. It also occurs if the VREG voltage falls below VREGMON, due to current exceeding IDSLIM. • Both input signal pins, ENB and ENBAT, are pulled low. This immediately pulls the NPOR pin low, indicating that the device is beginning a power-off sequence. In addition, the buck converter switching regulator is disabled, and the VREG supply begins to ramp down. The rate at which VREG decays is dependent on the total current draw, ILOAD, and value of the output capacitors (C1, C2, C3, and C4). • VREG drops below its UVLO threshold, VUVLOVREG. • During any normal power-on, VOUTVADJ falls below VUVLOVADJ, triggering a POR. An open drain output, through the NPOR pin, is provided to signal a POR event to the DSP or microcontroller. The reset occurs after an adjustable delay, tPOR, set by an external capaci- tor, C9, connected to the CPOR pin. The value of tPOR (ms) is calculated using the following formula tPOR = 2.13 ×105× CCPOR where CCPOR (µF) is the value of the C9 capacitor. A POR can be forced without a significant drop in the supply voltage, VREG, by pulsing low both the ENB and the ENBAT pins. However, pulse duration should be short enough so that VREG does not drop significantly. Thermal Shutdown. When the device junction temperature, TJ, is sensed to be at TJTSD (≈15°C higher than the thermal warning temperature, TJTW), a fault is indicated at the NFAULT pin. At the same time, a thermal shutdown circuit disables the buck converter, protecting the A8450 from damage. |
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