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XR16L2550IM Datasheet(PDF) 9 Page - Exar Corporation |
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XR16L2550IM Datasheet(HTML) 9 Page - Exar Corporation |
9 / 45 page áç áç áç áç XR16L2550 REV. 1.0.0 LOW VOLTAGE DUART WITH 16-BYTE FIFO 9 2.8 Crystal Oscillator or External Clock Input The L2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see “Programmable Baud Rate Generator.” The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 k Ω to 1 M Ω resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site. TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INTA/B Pin 0 = no data 1 = 1 byte 0 = FIFO below trigger level 1 = FIFO above trigger level FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS C1 22-47 pF C2 22-47 pF Y1 1.8432 MHz to 24 MHz R1 0-120 Ω (Optional) R2 500 Κ Ω − 1 Μ Ω XTAL1 XTAL2 |
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