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PNX1502G Datasheet(PDF) 6 Page - NXP Semiconductors |
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PNX1502G Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 100 page  Philips Semiconductors PNX15xx Series Volume 1 of 1 12NC 9397 750 14321 © Koninklijke Philips Electronics N.V. 2002-2003-2004. All rights reserved. Product data sheet Rev. 2 — 1 December 2004 -6 3.1 MMIO and Task Based Programming . . . . . 11-23 3.2 Setup Order for the QVCP . . . . . . . . . . . . . . . 11-24 3.2.1 Shadow Registers . . . . . . . . . . . . . . . . . . . . . . 11-25 3.2.2 Fast Access Registers . . . . . . . . . . . . . . . . . . . 11-29 3.3 Programming of Layer and Pool Resources 11-30 3.3.1 Resource Assignment and Selection . . . . . . 11-30 3.3.2 Aperture Assignment . . . . . . . . . . . . . . . . . . . . 11-30 3.3.3 Data Flow Selection . . . . . . . . . . . . . . . . . . . . . 11-32 3.3.4 Pool Resource Assignment Example . . . . . . 11-34 3.4 Programming the STG. . . . . . . . . . . . . . . . . . . 11-35 3.4.1 Changing Timing. . . . . . . . . . . . . . . . . . . . . . . . 11-36 3.5 Programming QVCP for Different Output Formats 11-36 4. Application Notes. . . . . . . . . . . . . . . . . . . . . . 11-37 4.1 Special Features. . . . . . . . . . . . . . . . . . . . . . . . 11-37 4.1.1 Signature Analysis . . . . . . . . . . . . . . . . . . . . . . 11-37 4.2 Programming Help . . . . . . . . . . . . . . . . . . . . . . 11-37 4.3 LINT Parameters . . . . . . . . . . . . . . . . . . . . . . . . 11-38 4.4 HSRU Parameters . . . . . . . . . . . . . . . . . . . . . . 11-38 4.5 LSHR Parameters . . . . . . . . . . . . . . . . . . . . . . . 11-39 4.6 DCTI Parameters . . . . . . . . . . . . . . . . . . . . . . . 11-40 4.7 CFTR Parameters . . . . . . . . . . . . . . . . . . . . . . . 11-40 4.8 Underflow Behavior . . . . . . . . . . . . . . . . . . . . . 11-40 4.8.1 Layer Underflow . . . . . . . . . . . . . . . . . . . . . . . . 11-41 4.8.2 Underflow Symptom . . . . . . . . . . . . . . . . . . . . . 11-41 4.8.3 Underflow Recovery . . . . . . . . . . . . . . . . . . . . . 11-41 4.8.4 Underflow Trouble-shooting . . . . . . . . . . . . . . 11-41 4.8.5 Underflow Handling . . . . . . . . . . . . . . . . . . . . . 11-41 4.9 Clock Calculations. . . . . . . . . . . . . . . . . . . . . . . 11-42 5. Register Descriptions . . . . . . . . . . . . . . . . . . 11-43 5.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . 11-43 5.2 Register Tables . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 Chapter 12: Video Input Processor 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 2. Functional Description . . . . . . . . . . . . . . . . . 12-2 2.1 VIP Block Level Diagram . . . . . . . . . . . . . . . . . 12-2 2.2 Chip I/O and Connections. . . . . . . . . . . . . . . . . 12-3 2.2.1 Data Routing and Video Modes . . . . . . . . . . . . 12-3 2.2.2 Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 2.3 Test Pattern Generator . . . . . . . . . . . . . . . . . . . 12-4 2.4 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 2.5 Video Data Path . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 2.5.1 Video Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 2.5.2 Video Data Acquisition . . . . . . . . . . . . . . . . . . . . 12-8 2.5.3 Internal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 2.5.4 Field Identifier Generation . . . . . . . . . . . . . . . . . 12-9 2.5.5 Horizontal Video Filters (Sampling, Scaling, Color Space Conversion)12-12 2.5.6 Video Data Write to Memory . . . . . . . . . . . . . . 12-13 2.5.7 Auxiliary Data Path . . . . . . . . . . . . . . . . . . . . . . 12-15 2.5.8 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . 12-19 3. Register Descriptions . . . . . . . . . . . . . . . . . . 12-19 3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . 12-19 3.2 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 Chapter 13: FGPO: Fast General Purpose Output 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 1.1 FGPO Overview . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 1.2 FGPO to VDO pin mapping . . . . . . . . . . . . . . . 13-3 1.3 DTL MMIO Interface . . . . . . . . . . . . . . . . . . . . . 13-3 1.4 Header Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 1.5 Data Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 1.6 Record Output Mode . . . . . . . . . . . . . . . . . . . . . 13-3 1.7 Message Passing Mode . . . . . . . . . . . . . . . . . . 13-4 2. Functional Description . . . . . . . . . . . . . . . . . 13-5 2.1 Stopping clk_fgpo for output flow control . . . . 13-6 2.2 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 2.3 Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 2.4 Sample (data) Size. . . . . . . . . . . . . . . . . . . . . . . 13-7 2.5 Record or Message Size. . . . . . . . . . . . . . . . . . 13-7 2.6 Records or Messages Per Buffer . . . . . . . . . . 13-7 2.7 Stride. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 2.8 Interrupt Events. . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 2.8.1 BUF1DONE and BUF2DONE Interrupts . . . . 13-8 2.8.2 THRESH1_REACHED and THRESH2_REACHED Interrupts13-8 2.8.3 UNDERRUN Interrupt . . . . . . . . . . . . . . . . . . . . 13-8 2.8.4 MBE Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 2.9 Record or Message Counters . . . . . . . . . . . . . . 13-9 2.10 Timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 2.11 Variable Length . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 2.12 Output Time Registers . . . . . . . . . . . . . . . . . . . 13-10 2.13 Double Buffer Operation . . . . . . . . . . . . . . . . . 13-10 2.14 Single Buffer Operation . . . . . . . . . . . . . . . . . . 13-11 3. Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 3.1 Both Operating Modes . . . . . . . . . . . . . . . . . . . 13-11 3.1.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 3.1.2 Interrupt Service Routines . . . . . . . . . . . . . . . . 13-12 3.1.3 Optimized DMA Transfers . . . . . . . . . . . . . . . . 13-12 3.1.4 Terminating DMA Transfers . . . . . . . . . . . . . . 13-12 3.1.5 Signal Edge Definitions . . . . . . . . . . . . . . . . . . 13-12 3.2 Message Passing Mode. . . . . . . . . . . . . . . . . . 13-13 3.3 PNX1300 Series Message Passing Mode . . 13-13 3.4 Record Output Mode . . . . . . . . . . . . . . . . . . . . 13-13 3.4.1 Record Synchronization Events . . . . . . . . . . . 13-14 3.4.2 Buffer Synchronization Events . . . . . . . . . . . . 13-14 4. Register Descriptions . . . . . . . . . . . . . . . . . . 13-15 4.1 Mode Register Setup . . . . . . . . . . . . . . . . . . . . 13-15 4.2 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . 13-20 |
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