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MN5572 Datasheet(PDF) 6 Page - Panasonic Semiconductor |
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MN5572 Datasheet(HTML) 6 Page - Panasonic Semiconductor |
6 / 28 page MN5572 6 SDF00008BEM I Pin Descriptions (continued) 2. Local 16 mode pin descriptions (continued) Pin Name I/O Description P1TCPOUT O Testing P2TCPOUT O Testing MIN5 I 5 V voltage reference P1VDD I Internal frequency multiplier PLL power supply (3.3 V) P2VDD I External phase compensation PLL power supply (3.3 V) VDD I Power supply (3.3 V) P1VSS Ground P2VSS Ground VSS Ground 3. PCI mode pin descriptions Pin Name I/O Description ICLOCK I Internal operating clock input PCICLK I PCI interface clock input NRST I Hardware reset (active low) NCBE[3 : 0] I PCI command/byte enable (active low) NFRAME I PCI cycle frame (active low) NIRDY I PCI initiator ready (active low) IDSEL I PCI initialization device select AD[31 : 16] I/O PCI address/data I/O (upper 16 bits) AD[15 : 0] I/O PCI address/data I/O (lower 16 bits) NDEVSEL O PCI target device select (active low) NTRDY O PCI target ready (active low) PAR I/O PCI parity I/O NSTOP O PCI stop (active low) NSERR O PCI system error NPERR O PCI parity error IFCFG I Interface mode setting (connect high) BUSSEL I Data bus width setting (connect high) CLKSEL[2 : 0] I Internal/external clock select PLNRESET I Internal PLL reset (active low) P1NPWD I Low power mode control for internal frequency multiplier PLL (active low) P1SEL[2 : 1] I Frequency selector for internal frequency multiplier PLL P2NPWD I Low power mode control for external phase compensation PLL (active low) OCLOCK O Unused |
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