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IDT70V658S10BC Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT70V658S10BC Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 23 page  IDT70V658S Preliminary High-Speed 3.3V 64K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(5) NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranted by device characterization, but is not production tested. 3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 5 for details. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5) Symbol Parameter 70V658S10 Com'l Only 70V658S12 Com'l & Ind 70V658S15 Com'l & Ind Unit Min. Max. Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACE Chip Enable Access Time(3) ____ 10 ____ 12 ____ 15 ns tABE Byte Enable Access Time(3) ____ 5 ____ 6 ____ 7ns tAOE Output Enable Access Time ____ 5 ____ 6 ____ 7ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time(1,2) 0 40608 ns tPU Chip Enable to Power Up Time(2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(2) ____ 10 ____ 10 ____ 15 ns tSOP Semaphore Flag Update Pulse ( OE or SEM) ____ 4 ____ 6 ____ 8ns tSAA Semaphore Address Access Time 3 10 3 12 3 20 ns 5613 tbl 12 Symbol Parameter 70V658S10 Com'l Only 70V658S12 Com'l & Ind 70V658S15 Com'l & Ind Unit Min. Max. Min. Max. Min. Max. WRITE CYCLE tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tEW Chip Enable to End-of-Write(3) 8 ____ 10 ____ 12 ____ ns tAW Address Valid to End-of-Write 8 ____ 10 ____ 12 ____ ns tAS Address Set-up Time(3) 0 ____ 0 ____ 0 ____ ns tWP Write Pulse Width 8 ____ 10 ____ 12 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ ns tDW Data Valid to End-of-Write 6 ____ 8 ____ 10 ____ ns tDH Data Hold Time(4) 0 ____ 0 ____ 0 ____ ns tWZ Write Enable to Output in High-Z(1,2) ____ 4 ____ 4 ____ 4ns tOW Output Active from End-of-Write(1,2,4) 0 ____ 0 ____ 0 ____ ns tSWRD SEM Flag Write to Read Time 5 ____ 5 ____ 5 ____ ns tSPS SEM Flag Contention Window 5 ____ 5 ____ 5 ____ ns 5613 tbl 13 |
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