CY62137CV25/30/33 MoBL®
CY62137CV MoBL®
Document #: 38-05201 Rev. *D
Page 5 of 13
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
Min.
Typ.[5]
Max.
Unit
VDR
VCC for Data Retention
1.5
Vccmax
V
ICCDR
Data Retention Current
VCC= 1.5V
CE > VCC – 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
LL
1
6
µA
SL
4
tCDR
[6]
Chip Deselect to Data Retention Time
0
ns
tR
[7]
Operation Recovery Time
tRC
ns
Data Retention Waveform[8]
Switching Characteristics Over the Operating Range[9]
Parameter
Description
55 ns
70 ns
Unit
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
55
70
ns
tAA
Address to Data Valid
55
70
ns
tOHA
Data Hold from Address Change
10
10
ns
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low-Z[10]
5
5
ns
tHZOE
OE HIGH to High-Z[10, 12]
20
25
ns
tLZCE
CE LOW to Low-Z[10]
10
10
ns
tHZCE
CE HIGH to High-Z[10, 12]
20
25
ns
tPU
CE LOW to Power-up
0
0
ns
tPD
CE HIGH to Power-down
55
70
ns
tDBE
BHE/BLE LOW to Data Valid
55
70
ns
tLZBE
[11]
BHE/BLE LOW to Low-Z[10]
5
5
ns
tHZBE
BHE/BLE HIGH to High-Z[10, 12]
20
25
ns
Write Cycle[13]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
Notes:
7.
Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs.
8.
BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
9.
Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for
any given device.
11.
If both byte enables are toggled together this value is 10 ns.
12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
VCC(min.)
VCC(min.)
tCDR
VDR > 1.5 V
DATA RETENTION MODE
tR
CE or
VCC
BHE.BLE
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