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SPCA701A Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

Part No. SPCA701A
Description  DIGITAL VIDEO ENCODER FOR VIDEOCD
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Sunplus Technology Co., Ltd.
4
Rev.: 0.2
1999.12.07
SPCA701A
Preliminary
Table 3. Configuration Register Settings
Mode Register
Name
set to 0
Set to 1
Comments
EFIELD
The VSYNC pin will output
normal vertical
synchronization signal.
The VSYNC pin will output field
signal.
Low at VSYNC pin for
even field, high for odd field
This is only used at
master mode.
PAL625
525-line operation will be
select
The 625-line operation will be
select
This is only used at
master mode
YCSWAP
Do not swap Y and Cr/Cb
Swap Y and Cr/Cb sequence
----
CLOCK TIMING
A clock signal with a frequency twice the luminance sampling rate must be present at the CLK pin.
All setup and
hold timing specifications are measured with respect to the rising edge of this signal.
PIXEL INPUT TIMING
PIXEL SEQUENCE
Multiplexed Y, Cb, and Cr data is input through the DATA[7:0] inputs.
By default, the input sequence for active
video pixels must be Cb0, Y0, Cr0, Y1, Cb2, Y2, Cr2, Y3, etc., in accordance with CCIR-656.
This pattern
begins during the first CLK period after the falling edge of HSYNC* (regardless of the setting of SLAVE/MASTER
mode).
The order of Cb and Cr can be reversed by setting the CBSWAP pin.
Figure 1 illustrates the timing.
If the pixel stream input to the SPCA701A is off by one CLK period, the SPCA701A can lock to the pixel stream
by setting the YCSWAP register.
This would solve the problem of having the Y and Cr/Cb pixels swapped.
Figure 1. Pix Sequence
Cbn
Cbn+2
Crn
Yn + 1
Yn
Crn
Crn+2
Cbn
Yn + 1
Yn
CLK(2)
HSYNC*(3)
P[7:0]
P[7:0]
CBSWAP(1)
0
1
Notes: (1). CBSWAP is pin 11.
(2). Pixel transitions must occur observing setup and hold timing about the rising edge of CLK.
(3). Pixel sequence will beging with Cbn at 4 x m clock periods following the falling edge of HSYNC*, when m
is an integer.




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