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UCC27223PWPG4 Datasheet(PDF) 6 Page - Texas Instruments |
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UCC27223PWPG4 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page UCC27223 SLUS558 − DECEMBER 2003 6 www.ti.com SIMPLIFIED BLOCK DIAGRAM NC ENBL VDD VLO PVLO 1 2 3 4 5 VLO REGULATOR + 3.82 V/3.7 V UVLO PREDICTIVE DELAY CONTROLLER 14 13 12 11 10 9 VHI G1 SWS SW G2S G2 AGND IN 6 7 PVLO PVLO 8 PGND VLO VLO 110 k Ω RENBL APPLICATION INFORMATION predictive gate drive technique The Predictive Gate Drive t technology utilizes a digital feedback system to detect body-diode conduction, and then adjusts the deadtime delays to minimize it. This system virtually eliminates the body-diode conduction time intervals for the synchronous MOSFET, while adjusting for different MOSFETs characteristics, propagation and load dependent delays. Maximum power stage efficiency is the end result. Two internal feedback loops in the predictive delay controller continuously adjusts the turn on delays for the two MOSFET gate drives G1 and G2. As shown in Figure 2, tON,G1 and tON,G2 are varied to provide minimum body-diode conduction in the synchronous rectifier MOSFET Q2. The turn-off delay for both G1 and G2, tOFF,G1 and tOFF,G2 are fixed by propagation delays internal to the device. The predictive delay controller is implemented using a digital control technique, and the time delays are therefore discrete. The turn-on delays, tON, G1 and tON, G2, are changed by a single step (typically 3 ns) every switching cycle. The minimum and maximum turn-on delays for G1 and G2 are specified in the electrical characteristics table. |
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