PALCE26V12H-20JC datasheet(1/21 Pages) AMD

Part #	PALCE26V12H-20JC

Description	28-Pin EE CMOS Versatile PAL Device

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Manufacturer	AMD [Advanced Micro Devices]

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Publication# 16072

Rev. E

Amendment /0

Issue Date: February 1996

2-306

PALCE26V12 Family

28-Pin EE CMOS Versatile PAL Device

FINAL

COM’L: H-7/10/15/20

IND: H-10/15/20

DISTINCTIVE CHARACTERISTICS

s 28-pin versatile PAL programmable logic

device architecture

s Electrically erasable CMOS technology

provides half power (only 115 mA) at high

speed (7.5 ns propagation delay)

s 14 dedicated inputs and 12 input/output

macrocells for architectural flexibility

s Macrocells can be registered or combinatorial,

and active high or active low

s Varied product term distribution allows up to

16 product terms per output

s Two clock inputs for independent functions

s Global asynchronous reset and synchronous

preset for initialization

s Register preload for testability and built-in

register reset on power-up

s Space-efficient 28-pin SKINNYDIP and PLCC

packages

s Center V

CC and GND pins to improve signal

characteristics

s Extensive third-party software and programmer

support through FusionPLD partners

GENERAL DESCRIPTION

The PALCE26V12 is a 28-pin version of the popular

PAL22V10 architecture. Built with low-power, high-

speed, electrically-erasable CMOS technology, the

PALCE26V12 offers many unique advantages.

Device logic is automatically configured according to

the user’s design specification. Design is simplified by

design software, allowing automatic creation of a

programming file based on Boolean or state equations.

The software can also be used to verify the design and

can provide test vectors for the programmed device.

The PALCE26V12 utilizes the familiar sum-of-products

(AND/OR) architecture that allows users to implement

complex logic functions easily and efficiently. Multiple

levels of combinatorial logic can always be reduced

to sum-of-products form, taking advantage of the

very wide input gates available in PAL devices. The

functions are programmed into the device through

electrically-erasable floating-gate cells in the AND logic

array and the macrocells. In the unprogrammed state,

all AND product terms float HIGH. If both true and

complement of any input are connected, the term will be

permanently LOW.

The product terms are connected to the fixed OR array

with a varied distribution from 8 to 16 across the outputs

(see Block Diagram). The OR sum of the products feeds

the output macrocell. Each macrocell can be pro-

grammed as registered or combinatorial, active high or

active low, with registered I/O possible. The flip-flop can

be clocked by one of two clock inputs. The output

configuration is determined by four bits controlling three

multiplexers in each macrocell.

AMD’s FusionPLD program allows PALCE26V12

designs to be implemented using a wide variety of

popular industry-standard design tools. By working

closely with the FusionPLD partners, AMD certifies that

the tools provide accurate, quality support. By ensuring

that third-party tools are available, costs are lowered

because a designer does not have to buy a complete set

of new tools for each device. The FusionPLD program

also greatly reduces design time since a designer can

use a tool that is already installed and familiar. Please

refer to the PLD Software Reference Guide for certified

development systems and the Programmer Reference

Guide for approved programmers.

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