Low-Power, Dual, 12-Bit Voltage-Output DACs

with Configurable Outputs

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3

ELECTRICAL CHARACTERISTICS—MAX5156 (continued)

Note 1: Accuracy is specified from code 10 to code 4095.

Note 4: SCLK minimum clock period includes rise and fall times.

Rail-to-rail (Note 2)

CONDITIONS

nV-s

5

Digital Crosstalk

nV-s

5

Digital Feedthrough

µs

25

Time Required to Exit Shutdown

µA

0

±0.1

Current into FBA or FBB

V

Output High Voltage

V

Output Voltage Swing

µs

15

Output Settling Time

V

0.13

0.40

Output Low Voltage

V/µs

0.75

SR

Voltage Output Slew Rate

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

(Note 4)

(Note 3)

(Note 3)

ns

40

SCLK Pulse Width Low

ns

40

SCLK Pulse Width High

ns

100

SCLK Clock Period

µA

0

±1

Reference Current in Shutdown

µA

2

10

Power-Supply Current in

Shutdown

mA

0.5

0.65

Power-Supply Current

V

4.5

5.5

Positive Supply Voltage

ns

40

DIN Setup Time

ns

0

SCLK Rise to CS Rise Hold Time

ns

40

CS Fall to SCLK Rise Setup Time

ns

80

SCLK Fall to DOUT Valid

Propagation Delay

ns

80

SCLK Rise to DOUT Valid

Propagation Delay

ns

0

DIN Hold Time

ns

100

CS Pulse Width High

ns

40

CS Rise to SCLK Rise Hold

ns

10

SCLK Rise to CS Fall Delay

DIGITAL OUTPUTS (DOUT, UPO)

DYNAMIC PERFORMANCE

POWER SUPPLIES

TIMING CHARACTERISTICS