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ICS2305MI-1H Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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ICS2305MI-1H Datasheet(HTML) 4 Page - Integrated Circuit Systems |
4 / 8 page 3.3 VOLT ZERO DELAY, LOW SKEW BUFFER MDS 2305 D 4 Revision 022505 In te gr ated Circuit Systems ● 5 25 Race Stree t, San Jose, CA 951 26 ● te l (40 8) 2 97-12 01 ● www.icst.com ICS2305 DC Electrical Characteristics ICS2305M-XX , VDD = 3.3 V ±10%, Ambient Temperature -40 to +85 °C(Industrial), (0-70°C Commercial) Note 1: When there is no clock signal present at CLKIN, the ICS2305 will enter power down mode. The PLL is stopped and the outputs are tri-state. AC Electrical Characteristics ICS2305M-1 , VDD=3.3 V ±10%, Ambient temperature -40 to +85 °C(Industrial), (0-70°C Commercial) Note 2: With VDD at a steady rate and valid input at CLKIN. Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 3.6 V Input High Voltage VIH 2V Input Low Voltage VIL 0.8 V Input Low Current IIL VIN = 0V 50 µA Input High Current IIH VIN = VDD 100 µA Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA 0.4 V Operating Supply Current IDD No Load 32 mA Power Down Supply Current CLKIN = 0, Note 1 12 µA Short Circuit Current IOS Each output ±50 mA Input Capacitance CIN CLKIN 5 pF Parameter Symbol Conditions Min. Typ. Max. Units Output Clock Frequency fIN 10 pF load 10 133 MHz Output Clock Frequency 30 pF load 10 100 MHz Output Rise Time tOR 0.8 to 2.0 V, outputs loaded 2.5 ns Output Fall Time tOF 2.0 to 0.8 V, outputs loaded 2.5 ns Output Clock Duty Cycle tDC measured at 1.4V, Fout=66.67 MHz 40 50 60 % Output Clock Duty Cycle tDC measured at 1.4V, Fout=50 MHz 45 50 55 % Device to Device Skew rising edges at VDD/2 700 ps Output to Output Skew rising edges at VDD/2 250 ps Input to Output Skew rising edges at VDD/2 ±350 ps Cycle to Cycle Jitter measured at 66.67M, outputs loaded 200 ps PLL Lock Time Note 2 1.0 ms |
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