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MACH211SP-14 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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MACH211SP-14 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 33 page MACH211SP-7/10/12/15 9 V ANTIS The Macrocell The MACH211SP has two types of macrocell: output and buried. The output macrocells can be configured as either registered, latched, or combinatorial, with programmable polarity. The macrocell provides internal feedback whether configured with or without the flip-flop. The registers can be configured as D-type or T-type, allowing for product-term optimization. The flip-flops can individually select one of two clock/gate pins, which are also available as data inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The latch holds its data when the gate input is HIGH, and is transparent when the gate input is LOW. The flip-flops can also be asynchronously initialized with the common asynchronous reset and preset product terms. The buried macrocells are the same as the output macrocells if they are used for generating logic. In that case, the only thing that distinguishes them from the output macrocells is the fact that there is no I/O cell connection, and the signal is only used internally. The buried macrocell can also be configured as an input register or latch. The I/O Cell The I/O cell in the MACH211SP consists of a three-state output buffer. The three-state buffer can be configured in one of three ways: always enabled, always disabled, or controlled by a product term. If product term control is chosen, one of two product terms may be used to provide the control. The two product terms that are available are common to all I/O cells in a PAL block. These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. SpeedLocking for Guaranteed Fixed Timing The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the central switch matrix, the MACH211SP product offers the SpeedLocking feature, which allows a stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to 16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking combine for continuous, high performance required in today's demanding designs. In-System Programming Programming is the process where MACH devices are loaded with a pattern defined in a JEDEC file obtained from MACHXL software or third-party software. Programming is accomplished through four JTAG pins: Test Mode Select (TMS), Test Clock (TCK), Test Data In (TDI), and Test Data Out (TDO). The MACH211SP can be deployed in any JTAG (IEEE 1149.1) compliant chain. While the MACH211SP is fully JTAG compatible, it supports the BYPASS instruction, not the EXTEST and SAMPLE/PRELOAD instructions. The MACH211SP can be programmed across the commercial temperature range. Programming the MACH device after it has been placed on a circuit board is easily accomplished. Programming is initiated by placing the device into programming mode, using the MACHPRO programming software provided by Vantis. The device is bulk erased and the JEDEC file is then loaded. After the data is transferred into the device, the PROGRAM instruction is loaded. |
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