FINAL

Publication# 20405

Rev: C

Amendment/0

Issue Date: August 1997

1

MACH 1 & 2 FAMILIES

1

COM’L: -7/10/12/15

IND: -10/12/14/18

MACH211SP-7/10/12/15

High-Performance EE CMOS

In-System Programmable Logic

DISTINCTIVE CHARACTERISTICS

x

JTAG-Compatible, 5-V in-system programming

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44 Pins in PLCC and TQFP

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64 Macrocells

x

x

x

32 I/Os; 2 dedicated inputs/clocks

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64 Flip-flops; 2 clock choices

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4 “PALCE26V16” blocks with buried macrocells

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Speed Locking™ for guaranteed fixed timing

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Bus-Friendly™ Inputs and I/Os

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Peripheral Component Interconnect (PCI) compliant (-7/-10/-12)

x

Programmable power-down mode

IN-SYSTEM PROGRAMMING

In-system programming allows the MACH211SP to be programmed while soldered onto a system

board. Programming the MACH211SP in-system yields numerous benefits at all stages of

development: prototyping, manufacturing, and in the field. Since insertion into a programmer isn’t

needed, multiple handling steps and the resulting bent leads are eliminated. The design can be

modified in-system for design changes and debugging while prototyping, programming boards in

production, and field upgrades.

extensive routing resources for pin-out retention; design changes resulting in pin-out changes

for many non-Vantis CPLDs cancel the advantages of in-system programming. The MACH211SP

can be deployed in any JTAG (IEEE 1149.1) compliant chain.

GENERAL DESCRIPTION

The MACH211SP is a member of Vantis’ high-performance EE CMOS MACH 1 & 2 families. This

device has approximately six times the logic macrocell capability of the popular PALCE22V10

without loss of speed.

The four PAL blocks are essentially “PALCE26V16” structures complete with product-term arrays

and programmable macrocells, which can be programmed as high speed or low power, and buried

macrocells. The switch matrix connects the PAL blocks to each other and to all input pins,