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IC42S16400-7T Datasheet(PDF) 27 Page - Integrated Circuit Solution Inc

Part # IC42S16400-7T
Description  1M x 16Bit x 4 Banks (64-MBIT) SDRAM
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Manufacturer  ICSI [Integrated Circuit Solution Inc]
Direct Link  http://www.icsi.com.tw
Logo ICSI - Integrated Circuit Solution Inc

IC42S16400-7T Datasheet(HTML) 27 Page - Integrated Circuit Solution Inc

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IC42S16400
Integrated Circuit Solution Inc.
27
DR034-0E 12/02/2003
Precharge Termination in WRITE Cycle
During WRITE cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command. The DQM must be high to mask
invalid data in.
During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid
data may be written at the same clock as the precharge command. To prevent this from happening, DQM must be high
at the same clock as the precharge command. This will mask the invalid data.
PRECHARGE TERMINATION in WRITE Cycle
Burst lengh = X
CLK
Command
CAS latency = 2
DQM
Hi - Z
Write
T0
T1
T2
T3
T4
T5
T6
T7
T8
tRP
PRE
ACT
DQ
Write
PRE
ACT
tRP
CAS latency = 3
Hi - Z
D0
D3
D2
D1
D0
D3
D2
D1
DQM
D4
D4
command
DQ


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