This Data Sheet may be revised by subsequent versions

©2003 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

9

EN29F010

Rev. A, Issue Date: 2003/10/20

Any commands written to the chip during the Embedded Erase algorithm are ignored.

The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write

Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,

the device returns to reading array data and addresses are no longer latched.

Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in

“AC Characteristics” for parameters, and Chip/Sector Erase Operation Timings for timing waveforms.

Sector Erase Command

Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two

un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the

address of the sector to be erased, and the sector erase command. The Command Definitions table

shows the address and data requirements for the sector erase command sequence.

The device does

algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical

erase. The system is not required to provide any controls or timings during these operations.

This device does not support multiple sector erase commands. Sector Erase operation will

commence immediately after the first 30h command is written. The first sector erase operation must

finish before another sector erase command can be given.

Once the sector erase operation has begun, only the Erase Suspend command is valid. All other

commands are ignored.

When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses

are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or

DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the

algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC

Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing

waveforms.

Erase Suspend / Resume Command

The Erase Suspend command allows the system to interrupt a sector erase operation and then read data

from, or program data to, any sector not selected for erasure. This command is valid only during the

sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation

or Embedded Program algorithm. Addresses are “don’t-cares” when writing the Erase Suspend command.

When the Erase Suspend command is written during a sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

After the erase operation has been suspended, the system can read array data from or program data to

any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)

Normal read and write timings and command definitions apply. Reading at any address within erase-

suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”

for information on these status bits.

After an erase-suspended program operation is complete, the system can once again read array data

within non-suspended sectors. The system can determine the status of the program operation using the

DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more

information.