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3D7428-1 Datasheet(PDF) 2 Page - Data Delay Devices, Inc. |
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3D7428-1 Datasheet(HTML) 2 Page - Data Delay Devices, Inc. |
2 / 7 page 3D7428 APPLICATION NOTES The inherent delay error is the deviation of the inherent delay from its nominal value. It is limited to 1.0 LSB or 2.0 ns, whichever is greater. GENERAL INFORMATION The 8-bit programmable 3D7428 delay line architecture is comprised of a number of delay cells connected in series with their respective outputs multiplexed onto the Delay Out pin (OUT) by the user-selected programming data (the address). Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The change in delay from one address setting to the next is called the increment, or LSB. It is nominally equal to the device dash number. The minimum delay, achieved by setting the address to zero, is called the inherent delay. DELAY STABILITY The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The 3D7428 utilizes novel compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature. With regard to stability, the delay of the 3D7428 at a given address, i, can be split into two components: the inherent delay (T0) and the relative delay (Ti – T0). These components exhibit very different stability coefficients, both of which must be considered in very critical applications. For best performance, it is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred. Also, signal traces should be kept as short as possible. The thermal coefficient of the relative delay is limited to ±250 PPM/C, which is equivalent to a variation, over the -40C to 85C operating range, of ±1.5% from the room-temperature delay settings. This holds for all dash numbers. The thermal coefficient of the inherent delay is nominally +10ps/C for dash numbers less than 1, and +15ps/C for all other dash numbers. DELAY ACCURACY There are a number of ways of characterizing the delay accuracy of a programmable line. The first is the differential nonlinearity (DNL), also referred to as the increment error. It is defined as the deviation of the increment at a given address from its nominal value. For most dash numbers, the DNL is within 0.5 LSB at every address (see Table 1: Delay Step). The power supply sensitivity of the relative delay is ±0.5% over the 4.75V to 5.25V operating range, with respect to the delay settings at the nominal 5.0V power supply. This holds for all dash numbers. The sensitivity of the inherent delay is nominally –1ps/mV for all dash numbers. The integrated nonlinearity (INL) is determined by first constructing the least-squares best fit straight line through the delay-versus-address data. The INL is then the deviation of a given delay from this line. For all dash numbers, the INL is within 1.0 LSB at every address. INPUT SIGNAL CHARACTERISTICS The frequency and/or pulse width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a recommended maximum and an absolute maximum operating input frequency and a recommended minimum and an absolute minimum operating pulse width have been specified. The relative error is defined as follows: erel = (Ti – T0) – i * Tinc where i is the address, Ti is the measured delay at the i’th address, T0 is the measured inherent delay, and Tinc is the nominal increment. It is very similar to the INL, but simpler to calculate. For most dash numbers, the relative error is less than 1.0 LSB at every address (see Table 1: Delay Range). OPERATING FREQUENCY The absolute maximum operating frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle The absolute error is defined as follows: eabs = Ti – (Tinh + i * Tinc) where Tinh is the nominal inherent delay. The absolute error is limited to 1.5 LSB or 3.0 ns, whichever is greater, at every address. Doc #03003 DATA DELAY DEVICES, INC. 2 11/1/04 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |
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