TLF5345

January 1988

MM54HC646MM74HC646 Non-Inverting

Octal Bus TransceiverRegisters

MM54HC648MM74HC648

Inverting Octal Bus TransceiverRegisters

General Description

These transceivers utilize advanced silicon-gate CMOS

technology and contain two sets of TRI-STATE

outputs

two sets of D-type flip-flops and control circuitry designed

for high speed multiplexed transmission of data

Six control inputs enable this device to be used as a latched

transceiver unlatched transceiver or a combination of both

As a latched transceiver data from one bus is stored for

later retrieval by the other bus Alternately real time bus

data (unlatched) may be directly transferred from one bus to

another

Circuit operation is determined by the G DIR CAB CBA

SAB SBA control inputs The enable input G controls

whether any bus outputs are enabled The direction control

DIR determines which bus is enabled and hence the direc-

tion data flows The SAB SBA inputs control whether the

latched data (stored in D type flip flops) or the bus data

(from other bus input pins) is transferred Each set of flip-

flops has its own clock CAB and CBA for storing data Data

is latched on the rising edge of the clock

Each output can drive up to 15 low power Schottky TTL

loads These devices are functionally and pin compatible to

their LS-TTL counterparts All inputs are protected from

ground

Features

Y

Typical propagation delay 14 ns

Y

TRI-STATE outputs

Y

Bidirectional communication

Y

Wide power supply range 2 – 6V

Y

Low quiescent supply current 160 mA

maximum (74HC)

Y

High output current 6 mA (74HC)

Connection Diagram

Dual-In-Line Package

TLF5345 – 2

Order Number MM54HC646648 or

MM74HC646648

TLF5345 – 1

Real-Time Transfer

Bus B to Bus A

Real-Time Transfer

Bus A to Bus B

Storage from

A B or A and B

Transfer Stored Data

toAorB

TRI-STATE

is a registered trademark of National Semiconductor Corp

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A