11

COMMERCIALANDINDUSTRIALTEMPERATURERANGE

IDT72V275/72V285

SIGNAL DESCRIPTION

INPUTS:

Data inputs for 18-bit wide data.

CONTROLS:

MASTER RESET (

MRS

MRS

MRS

MRS

MRS)

A Master Reset is accomplished whenever the

MRS input is taken to

a LOW state. This operation sets the internal read and write pointers to the

first location of the RAM array.

PAE will go LOW, PAF will go HIGH, and

HF will go HIGH.

If FWFT is LOW during Master Reset then the IDT Standard mode,

along with

EF and FF are selected. EF will go LOW and FF will go HIGH.

If FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with

IR and OR, are selected. OR will go HIGH and IR will go LOW.

If

LD is LOW during Master Reset, then PAE is assigned a threshold

127 words from the empty boundary and

PAF is assigned a threshold 127

words from the full boundary; 127 words corresponds to an offset value of

07FH. Following Master Reset, parallel loading of the offsets is permitted,

but not serial loading.

If

LD is HIGH during Master Reset, then PAE is assigned a threshold

1,023 words from the empty boundary and

PAF is assigned a threshold

1,023 words from the full boundary; 1,023 words corresponds to an offset

value of 3FFH. Following Master Reset, serial loading of the offsets is

permitted, but not parallel loading.

Parallel reading of the registers is always permitted. (See section

describing the

LD pin for further details.)

During a Master Reset, the output register is initialized to all zeroes. A

Master Reset is required after power up, before a write operation can take

place.

MRS is asynchronous.

See Figure 5, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET (

PRS

PRS

PRS

PRS

PRS)

A Partial Reset is accomplished whenever the

PRS input is taken to a LOW

state. As in the case of the Master Reset, the internal read and write pointers are

set to the first location of the RAM array,

PAE goes LOW, PAF goes HIGH, and

HF goes HIGH.

Whichever mode is active at the time of Partial Reset, IDT Standard mode

or First Word Fall Through, that mode will remain selected. If the IDT Standard

mode is active, then

FF will go HIGH and EF will go LOW. If the First Word

Fall Through mode is active, then

OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. The programming method (parallel or serial) currently active

at the time of Partial Reset is also retained. The output register is initialized

to all zeroes.

PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of

operation, when reprogramming partial flag offset settings may not be

convenient.

See Figure 6, Partial Reset Timing, for the relevant timing diagram.

RETRANSMIT (

RT

RT

RT

RT

RT)

The Retransmit operation allows data that has already been read to be

accessed again. There are two stages: first, a setup procedure that resets the

read pointer to the first location of memory, then the actual retransmit, which

consists of reading out the memory contents, starting at the beginning of the

memory.

Retransmitsetupisinitiatedbyholding

RTLOWduringarising RCLKedge.

REN and WEN must be HIGH before bringing RT LOW.

If IDT Standard mode is selected, the FIFO will mark the beginning of

the Retransmit setup by setting

EF LOW. The change in level will only be

noticeable if

EF was HIGH before setup. During this period, the internal

read pointer is initialized to the first location of the RAM array.

When

EF goes HIGH, Retransmit setup is complete and read opera-

tions may begin starting with the first location in memory. Since IDT

Standard mode is selected, every word read including the first word

following Retransmit setup requires a LOW on

REN to enable the rising

edge of RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for

the relevant timing diagram.

If FWFT mode is selected, the FIFO will mark the beginning of the Retransmit

setup by setting

OR HIGH. During this period, the internal read pointer is set to

the first location of the RAM array.

When

OR goes LOW, Retransmit setup is complete; at the same time,

the contents of the first location appear on the outputs. Since FWFT mode

is selected, the first word appears on the outputs, no LOW on

REN is

necessary. Reading all subsequent words requires a LOW on

REN to

enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT

Mode), for the relevant timing diagram.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state of the FWFT/SI

input determines whether the device will operate in IDT Standard mode or First

Word Fall Through (FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard

mode will be selected. This mode uses the Empty Flag (

EF) to indicate

whether or not there are any words present in the FIFO memory. It also uses

the Full Flag function (

FF) to indicate whether or not the FIFO memory has

any free space for writing. In IDT Standard mode, every word read from the

FIFO, including the first, must be requested using the Read Enable (

REN)

and RCLK.

If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will

be selected. This mode uses Output Ready (

OR) to indicate whether or not

IR)

to indicate whether or not the FIFO memory has any free space for writing.

In the FWFT mode, the first word written to an empty FIFO goes directly to

REN = LOW is not necessary. Subse-

quent words must be accessed using the Read Enable (

REN) and RCLK.

After Master Reset, FWFT/SI acts as a serial input for loading

PAE and

PAF offsets into the programmable registers. The serial input function can

only be used when the serial loading method has been selected during

Master Reset. Serial programming using the FWFT/SI pin functions the

same way in both IDT Standard and FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the WCLK input. Data setup

and hold times must be met with respect to the LOW-to-HIGH transition of

the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle,

the

FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only

capable of updating

HFflagtoLOW.) TheWriteandReadClockscaneither

be independent or coincident.

WRITE ENABLE (

WEN

WEN

WEN

WEN

WEN)

When the

WEN input is LOW, data may be loaded into the FIFO RAM

array on the rising edge of every WCLK cycle if the device is not full. Data

is stored in the RAM array sequentially and independently of any ongoing

read operation.